ATMEGA64-16AI datasheet(13/393 Pages) ATMEL

13 / 393 page

ATmega64(L)

2490L–AVR–10/06

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc-

tion Set Description” for detailed information.

General Purpose

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to

achieve the required performance and flexibility, the following input/output schemes are

supported by the Register File:

•

One 8-bit output operand and one 8-bit result input.

•

Two 8-bit output operands and one 8-bit result input.

•

Two 8-bit output operands and one 16-bit result input.

•

One 16-bit output operand and one 16-bit result input.

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers,

and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user data space. Although not being physi-

cally implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to

index any register in the file.

Addr.

0x00

0x01

0x02

…

R13

0x0D

General

R14

0x0E

Purpose

R15

0x0F

Working

R16

0x10

Registers

R17

0x11

…

R26

0x1A

X-register Low Byte

R27

0x1B

X-register High Byte

R28

0x1C

Y-register Low Byte

R29

0x1D

Y-register High Byte

R30

0x1E

Z-register Low Byte

R31

0x1F

Z-register High Byte

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