AMC131M02DFMR datasheet(33/89 Pages) TI

номер детали	AMC131M02DFMR

подробное описание детали	AMC131M02 2-Channel, 64-kSPS, Simultaneous-Sampling, 24-Bit, Reinforced Isolated Delta-Sigma ADC With Integrated DC/DC Converter

PDF	89 Pages

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производитель	TI [Texas Instruments]

домашняя страница	http://www.ti.com

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Regarding the conversion data after power-up, pay attention to the following:

• The high-to-low transition of DRDY indicates that new conversion data are available. As given in Figure 8-16,

ADC data are only valid if the SEC_FAIL reads 0b during the conversion period. The first two conversion

results shown in Figure 8-16, represent invalid data.

• When the ADC generates valid data, the digital filter must settle, as described in the SINC3 and SINC3 +

SINC1 Filter section. Two subsequent conversion results illustrated in Figure 8-16 are unsettled (assuming

OSR equals 1024), and the last conversion result shown provides valid and settled data.

• For best control of the conversion timing, especially in a system where multiple devices of the AMC131M02

are used, trigger a synchronization using the SYNC/RESET pin before the host collects conversion data from

the ADC. See the Synchronization section for more details regarding how to synchronize the device.

In Figure 8-16, tPOR_SEC is the time from enabling the DC/DC converter to the first falling edge of the SEC_FAIL

bit, which indicates that the secondary power supply at the HLDO_OUT pin is stable. tPOR_DVDD is the time from

DVDD supply at 90% to DRDY first rising edge.

tPOR_DVDD

Invalid data

Unsettled

filter data

Unsettled

filter data

Valid Sinc

filter data

tDATA

...

DVDD

90%

DRDY

CLKIN

SEC_FAIL

HLDO_OUT

90%

tPOR_SEC

...

SPI write to

configure

registers

Invalid data

tDATA

Figure 8-16. Start-Up Behavior at Power-Up and Settling Times, OSR = 1024

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AMC131M02

SBASA56 – SEPTEMBER 2023

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