WM8718

Production Data

w

PD Rev 4.3 November 2006

22

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0011

Format Control

4

LRP

0

DSP Format (DSP modes)

0: Late DSP mode

1: Early DSP mode

Table 7 DSP Format Control

In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that

detects a low to high transition on LRCIN. In DSP late mode, the first bit is sampled on the

BCKIN rising edge, which detects a low to high transition on LRCIN. No BCKIN edges are allowed

between the data words. The word order is DIN left, DIN right.

ATTENUATOR CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both left

and right channel DACs from the next audio input sample. No update to the attenuation registers

is required for ATC to take effect. (The right channels registry settings are preserved.)

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0011

PCM Control

5

ATC

0

Attenuator Control Mode:

0:

Right channels use Right

attenuation

1:

Right Channels use Left

Attenuation

Table 8 Attenuation Control Select

BCKIN POLARITY

By default, LRCIN and DIN are sampled on the rising edge of BCKIN and should ideally change

on the falling edge. Data sources which change LRCIN and DIN on the rising edge of BCKIN can

be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the

inverse of that shown in Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0011

PCM Control

6

BCP

0

BCKIN

0: normal polarity

1: inverted polarity

Table 9 BCKIN Polarity Control

OUTPUT PHASE REVERSAL

The REV register bit controls the phase of the output signal. Setting the REV bit causes the

phase of the output signal to be inverted.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0011

PCM Control

7

REV

0

Analogue Output Phase

0: Normal

1: Inverted

Table 10 Output Phase Control