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WM8718SEDS/R датащи(PDF) 15 Page - Wolfson Microelectronics plc

номер детали WM8718SEDS/R
подробное описание детали  24 Bit Differential Stereo DAC with Volume Control
PDF  32 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8718SEDS/R датащи(HTML) 15 Page - Wolfson Microelectronics plc

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WM8718
Production Data
w
PD Rev 4.3 November 2006
15
The WM8718 will automatically detect when data with a LRCIN period of exactly 32 BCKINs is
sent, and select 16-bit mode - overriding any previously programmed word length. Word length
will revert to a programmed value only if a LRCIN period other than 32 BCKINs is detected.
In DSP Mode A or DSP Mode B, the data is time multiplexed onto DIN. LRCIN is used as a
frame sync signal to identify the MSB of the first word. The minimum number of BCKINs per
LRCIN period is 2 times the selected word length. Any mark to space ratio is acceptable on
LRCIN provided the rising edge is correctly positioned. (See Figure 10 and Figure 11)
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN
transition. LRCIN is high during the left data word and low during the right data word.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 7 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left data word and low during the right data word.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 8 Right Justified Mode Timing Diagram
I
2S MODE
In I
2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left data word and high during the right data word.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
1 BCKIN
1 BCKIN
Figure 9 I
2S Mode Timing Diagram



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