WM8718

Production Data

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PD Rev 4.3 November 2006

19

REGISTER

ADDRESS

(A3,A2,A1,A0)

BITS

NAME

DEFAULT

DESCRIPTION

[3:2]

FMT[1:0]

10

Audio Data Format Select.

00: right justified mode

01: left justified mode

10: I

11: DSP mode

4

LRP

0

Polarity Select for LRCIN/DSP Mode Select.

0: normal LRCIN polarity/DSP late mode

1: inverted LRCIN polarity/DSP early mode

5

ATC

0

Attenuator Control.

0: All DACs use attenuation as programmed.

1: Right channel DACs use corresponding left DAC

attenuation

6

BCP

0

BCKIN Polarity

0: normal polarity

1: inverted polarity

7

REV

0

Output Phase Reversal, see Table 10

Table 3 Register Bit Descriptions

ATTENUATION CONTROL

Each DAC channel can be attenuated digitally before being applied to the digital filter.

Attenuation is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8

Attenuation control bits. All attenuation registers are double latched allowing new values to be

pre-latched to both channels before being updated synchronously. Setting the UPDATE bit on

any attenuation write will cause all pre-latched values to be immediately applied to the DAC

channels.

REGISTER

ADDRESS

BITS

LABEL

DEFAULT

DESCRIPTION

[7:0]

LAT[7:0]

11111111 (0dB)

Attenuation data for Left Channel DACL in 0.5dB steps.

0000

Attenuation

DACL

8

UPDATEL

0

Controls simultaneous update of all Attenuation Latches

0: Store DACL in intermediate latch (no change to output)

1: Store DACL and update attenuation on all channels.

[7:0]

RAT[7:0]

11111111 (0dB)

Attenuation data for Right channel DACR in 0.5dB steps.

0001

Attenuation

DACR

8

UPDATER

0

Controls simultaneous update of all Attenuation Latches

0: Store DACR in intermediate latch (no change to output)

1: Store DACR and update attenuation on all channels.

Table 4 Attenuation Register Map

Note:

1.

The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the

relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next input

sample.

2.

Care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise if the ZCDINIT

register bit has been set, (disabled).