VSC8541-02 datasheet(49/101 Pages) MICROCHIP

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Registers

VMDS-10513 VSC8541-02 Datasheet Revision 4.1

The following information applies to the extended control and status bits:

•

When bit 22.15 is set, the link integrity state machine is bypassed and the PHY is forced into a link

pass status.

•

When bits 22.11:10 are set to 00, the squelch threshold levels are based on the IEEE standard for

10BASE-T. When set to 01, the squelch level is decreased, which can improve the bit error rate

performance on long loops. When set to 10, the squelch level is increased and can improve the bit

error rate in high-noise environments.

•

When bit 22.9 is set, all sticky register bits retain their values during a software reset. Clearing this

bit causes all sticky register bits to change to their default values upon software reset. Super-sticky

bits retain their values upon software reset regardless of the setting of bit 22.9.

•

When bit 22.0 is set, if a write to any PHY register (registers 0–31, including extended registers), the

same write is broadcast to all PHYs. For example, if bit 22.0 is set to 1 and a write to PHY0 is

executed (register 0 is set to 0x1040), all PHYs' register 0s are set to 0x1040. Disabling this bit

restores normal PHY write operation. Reads are still possible when this bit is set, but the value that

is read corresponds only to the particular PHY being addressed.

4.2.21

Extended PHY Control 1

The following table shows the settings available.

Note: After configuring bits 13:11 of the extended PHY control register set 1, a software reset (register 0, bit 15)

must be written to change the device operating mode. On read, these bits only indicate the actual

operating mode and not the pending operating mode setting before a software reset has taken place.

SMI broadcast write

R/W

Sticky bit.

1: Enabled.

Table 42 •

Extended PHY Control 1, Address 23 (0x17)

Bit

Name

Access Description

Default

15:14 Reserved

Reserved.

MAC supplied clock

enable

R/W

MAC interface RX_CLK synchronization.

0: Synchronize RX_CLK to recovered clock.

1: Synchronize RX_CLK to REFCLK.

Note: This bit is not applicable to the RMII MAC

interface selection. This bit may be

changed during COMA mode or written

prior to a soft-reset, after which it takes

effect.

12:11

MAC interface selection R/W

MAC interface mode.

00: GMII/MII.

01: RMII.

10: RGMII.

11: Reserved.

Note: These bits may be changed during

COMA mode or written prior to a soft-

reset, after which it takes effect.

10:4

Reserved

Reserved.

Far-end loopback mode R/W

1: Enabled.

2:0

Reserved

Reserved.

Table 41 •

Extended Control and Status, Address 22 (0x16) (continued)

Bit

Name

Access Description

Default

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