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TMS320C32PCMA50 датащи(PDF) 33 Page - Texas Instruments |
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TMS320C32PCMA50 датащи(HTML) 33 Page - Texas Instruments |
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33 / 45 page ![]() TMS320C32 DIGITAL SIGNAL PROCESSOR SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996 33 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing for INT3 –INT0 interrupt response [P = tc(H)] (see Figure 27) NO ’C32 - 40 ’C32 - 50 ’C32 - 60 UNIT NO. MIN MAX MIN MAX MIN MAX UNIT 61 tsu(INT) Setup time, INT3–INT0 before H1 low 13 10 8 ns 62.1 tw(INT) Pulse duration of interrupt to assure only one interrupt seen for level-triggered interrupts P 2P† P 2P† P 2P† ns 62.2 tw(INT) Pulse duration of interrupt for edge-triggered interrupts P† P† P† ns † Assured from characterization but not tested. First Instruction Address Reset or Interrupt Vector Read Fetch First Instruction of Service Routine H3 H1 INT3 – INT0 Pin INT3 – INT0 Flag A D Vector Address 61 62.1 62.2 Figure 27. INT3–INT0 Interrupt-Response Timing |
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