TAS5504_06 datasheet(69/96 Pages) TI

69 / 96 page

Serial Control Interface Register Definitions

SLES123 − October 2004

TAS5504

Serial Control Interface Register Definitions

Unless otherwise noted, the I2C register default values are in bold font.

Note that u indicates unused bits.

6.1

Clock Control Register (0x00)

Bit D1 is Don’t Care.

Table 6−1. Clock Control Register

FUNCTION

−

32-kHz data rate

−

38-kHz data rate

−

44.1-kHz data rate

−

48-kHz data rate

−

88.2-kHz data rate

−

96-kHz data rate

−

176.4-kHz data rate

−

192-kHz data rate

−

MCLK frequency = 64

−

MCLK frequency = 128

−

MCLK frequency = 192

−

MCLK frequency = 256

−

MCLK frequency = 384

−

MCLK frequency = 512

−

MCLK frequency = 768

−

Reserved

−

Clock register is valid (read only)

−

Clock register is not valid (read only)

6.2

General Status Register 0 (0x01)

Table 6−2. General Status Register (0x01)

FUNCTION

−

Clip indicator

−

Bank switching busy

−

Identification code for TAS5504

6.3

Error Status Register (0x02)

Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must

clear the register (write zeroes) and than read them to determine if there are any persistent errors.

Table 6−3. Error Status Register (0X02)

FUNCTION

−

PLL phase lock error

−

PLL auto lock error

−

SCLK error

−

LRCLK error

−

Frame slip

No errors

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