TAS5504_06 datasheet(64/96 Pages) TI

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Serial Control I2C Register Summary

SLES123 − October 2004

TAS5504

Serial Control I2C Register Summary

The TAS5504 slave address is 0x36. See the Serial Control I2C Register Bit Definitions chapter for complete

bit definitions.

Note that u indicates unused bits.

I2C

SUBADDRESS

TOTAL

BYTES

DESCRIPTION OF CONTENTS

DEFAULT STATE

0x00

Clock control register

Set data rate and MCLK frequency

1. Fs = 48 kHz

2. MCLK = 256 Fs = 12.288 MHz

0x01

General status register

Clip indicator and ID code for the

TAS5504

0x01

0x02

Error status register

PLL, SCLK, LRCLK, and frame slip

errors

No errors

0x03

System control register 1

PWM high pass, clock set, un-mute

select, PSVC select

1. PWM high pass disabled

2. Auto clock set

3. Hard un-mute on clock error

recovery

4. PSVC HIZ disable

0x04

System control register 2

Automute and de-emphasis control

1. Automute timeout disable

2. Post-DAP detection automute

enabled

3. 4-Ch device input detection

automute enabled

4. Un-mute threshold 6 dB over input

5. No de-emphasis

0x05 – 0x06

Channel configuration registers Configure channels 1 and 2

1. Enable backend reset

2. Valid low for reset

3. Valid low for mute

4. Normal BEPolarity

5. Don’t remap the output for the

TAS5182

6. Don’t go low-low in mute

7. Don’t remap Hi-Z state to

low-low state

0x07 – 0x0A

Reserved

0x0B – 0x0C

Channel configuration registers Configure channels 3 and 4

1. Enable backend reset2. Valid

low for reset3. Valid low for mute4.

Normal BEPolarity5. Don’t remap

the output for the TAS51826. Don’t

go low-low in mute7. Don’t remap

Hi-Z state to low-low state

0x0D

Headphone configuration

Configure headphone output

1. Disable backend reset sequence

2 Valid does not have to be low for

reset

3. Valid does not have to be low for

mute

4. Normal BEPolarity

5. Don’t remap output to comply

with 5182

6. Don’t go low-low in mute

7. Don’t remap Hi−Z state to

low-low state

0x0E

Serial data interface register

Set serial data interface to right

justified, I2S, or left justified

24-bit I2S

0x0F

Soft mute register

Soft mute for channels 1, 2, 3, and 4

Un-mute all channels

0x10 – 0x13

RESERVED

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