MPF42791 datasheet(13/75 Pages) MPS

13 / 75 page

MPF42791 – 2 TO 16 BATTERY PACK FG W/ R DETECTION AND THERMAL MODEL

MPF42791 Rev. 1.0

MonolithicPower.com

9/19/2022

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

SDA line low. If the SDA line remains high during

the

acknowledge

clock

pulse,

not

acknowledged (NACK). Then the master can

generate a stop command to abort the transfer,

or it can generate a repeated start (Sr) command

to start a new transfer.

After the start command, a 7-bit slave address is

sent, followed by the read/write (R/W) bit. A 0

represents a write transmission (W), while a 1

indicates a read request (R). Figure 9 shows a

complete data transfer.

Figure 9: Complete Data Transfer

Active Mode

The MPF42791 must be in active mode to

communicate

(see

Operating

Modes

for

additional detail). To transition to active mode,

the SDA line must be pulled low. There is a 20ms

timeout before starting operation, or the device

transitions back to standby mode. After the

operations

are

completed

(e.g.

I2C

communication or fuel gauge updates) there is a

5ms timeout.

low

5ms

pulse

the

SDA

line

recommended to transition to active mode. Note

that it may take a few additional milliseconds for

the MPF42791 to reach active mode and for the

I2C to be ready. To verify that the MPF42791 is

ready for communication, an I2C header with the

start command, the device address, and the R/W

bit can be sent. The device responds with an

ACK signal if it is ready for communication.

Protocol Layer

The MPF42791 uses a protocol where 2 bytes

are

used

for

the

and

command

addresses. A length field is also provided to

declare the number of bytes in each read or write

transaction. The maximum allowed transaction

length is 82 bytes of data (not including the

A Cyclic Redundancy Check (CRC) can be used

to ensure the transaction’s integrity. When

enabled, the last 4 bytes of the transaction

correspond to the CRC. Figure 10 and Figure 11

show an example of read and write transactions

with CRC, respectively.

Figure 10: I2C Read Transaction with CRC

Figure 11: I2C Write Transaction with CRC

If CRC is disabled, a write transaction can

optionally include the correct CRC bytes to be

accepted. During a read, the MPF42791 does

not include the CRC, so the NACK signal and

stop command from the master come after

DATA[x].

I2C operations using any address outside of the

valid addresses. An invalid read operation

returns a 0 as the data and correct CRC (if

enabled), and an invalid write operation is

ignored.

Cyclic Redundancy Check (CRC)

The CRC spans the register address, length, and

data payload. It is generated in blocks of 4 bytes.

If the number of bytes is not a multiple of 4, the

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