CS5535 datasheet(169/555 Pages) NSC

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4.18 FLASH CONTROLLER

The CS5535 has a Flash device interface that supports

popular NOR Flash and inexpensive NAND Flash devices.

This interface is shared with the IDE interface (ATA-5 Con-

troller (ATAC)), using the same balls. NOR or NAND Flash

may co-exist with IDE devices using PIO (Programmed I/O)

mode. The 8-bit interface supports up to four “lanes” of

byte-wide Flash devices through use of four independent

chip selects, and allows for booting from the array. Hard-

ware support is present for SmartMedia-type ECC (Error

Correction Code) calculations, off-loading software from

having to support this task.

Features

• Supports popular NOR Flash and inexpensive NAND

Flash devices on IDE interface. No extra pins needed.

• NOR Flash and NAND Flash co-exist with IDE devices

with PIO (Programmed I/O) only mode.

• General purpose chip select pins support on-board ISA-

like slave devices.

• Programmable timing supports a variety of Flash

devices.

• Supports up to four byte-wide NOR Flash devices.

— Address up to 256 kB boot ROMs using an external

octal latch.

— Address up to 256 MB linear Flash memory arrays

using external latches.

— Boot ROM capability.

— Burst mode capability (DWORD read/write on PCI

bus).

• Supports up to four byte-wide NAND Flash devices.

— Hardware support for SmartMedia-type ECC (Error

Correction Code) calculation off-loading software

effort.

• Supports four programmable chip select pins with

memory or I/O addressable.

— Up to 1 kB of address space without external latch.

4.18.1 NAND Flash Controller

To understand the functioning of the NAND Flash Control-

ler, an initialization sequence and a read sequence is pro-

vided in the following sub-sections. The NAND Flash

Controller’s registers can be mapped to memory or I/O

space. The following example is based on memory

mapped registers.

4.18.1.1 Initialization

Program MSR_LBAR_FLSH0 (MSR 51400010h) to

establish

base

address

(NAND_START)

and

whether in memory or I/O space. The NAND Controller

is memory mapped in this example and always occu-

pies 4 kB of memory space.

Set the NAND timing MSRs to the appropriate values

(MSRs 5140001Bh and 5140001Ch).

4.18.1.2 Read

Allocate a memory buffer. Start at address BAh in sys-

tem memory.

Fill the buffer with the following values:

– BA: 02h (Assert CE#, CLE)

– BA + 1: 00h (Command: Read mode)

– BA + 2: 04h (Assert CE#, ALE, De-assert CLE)

– BA + 3: CA (Start column address)

– BA + 4: 04h

– BA + 5: PA0 (Page address byte 0)

– BA + 6: 04h

– BA + 7: PA1 (Page address byte 1)

– BA + 8: 04h

– BA + 9: PA2 (Page address byte 2)

– BA + 10: 08h (Assert CE#, De-assert ALE, Enable

Interrupt)

For (i = 0; i < 11; i++), write the data in buffer [BA+i] to

memory location [NAND_START + 800h + i]. Generate

the command and address phase on the NAND Flash

interface.

NAND Flash device may pull down the RDY/BUSY#

signal at this point. Software sets the EN_INT bit and

waits for the interrupt.

Memory

byte

writes

03h

memory

location

[NAND_START + 815h] to clear ECC parity and

Enable ECC engine.

For (i = 0; i < 256; i++), read data from [NAND_START

+ i] to buffer [BA + i] (read data from NAND Flash to

memory buffer. Can use DWORD read to save time).

Memory DWORD Reads [NAND_START + 810h] to

get ECC parity [ECC0] of first 256 byte data.

Memory

byte

writes

03h

memory

location

[NAND_START + 815h] to clear ECC parity and

enable ECC engine.

For (i = 256; i < 512; i++), read data from

[NAND_START + i] to buffer [BA + i] (read data from

NAND Flash to memory buffer. Can use DWORD read

to save time).

10) Memory DWORD reads [NAND_START + 810h] to get

ECC parity [ECC1] of second 256 byte data.

11) For (i = 512; i < 528; i++), read data from

[NAND_START + i] to buffer [BA + i] (read data from

NAND Flash redundant data to memory buffer. Can

use DWORD read to save time).

12) Write 01h to memory location [NAND_START + 800h]

(de-assert CE#, NAND Flash enters to Idle state).

13) Retrieve ECC parity data from redundant data area

and compare them to ECC0 and ECC1.

14) Correct data if data error is detected and can be fixed.

Figure 4-56 on page 170 shows a basic NAND read cycle.

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