CS5535 datasheet(171/555 Pages) NSC

171 / 555 page

Revision 0.8

171

www.national.com

Flash Controller Functional Description (Continued)

Software Operation

The NAND Flash contains a redundant data area contain-

ing ECC fields. While writing to the NAND Flash, the hard-

ware ECC engine calculates ECC parity, if it is enabled

properly. Software can write the ECC parity bits to the ECC

field after writing the data area. When software reads the

data from NAND Flash, the hardware ECC engine calcu-

lates ECC parity. After the data is read from the NAND

Flash, software can compare the ECC parity in the hard-

ware ECC engine and the ECC parity in the ECC field of

the NAND Flash to determine if the data block is correct.

Each data bit has 11 corresponding parity bits, which can

be determined by the bit address. If one data bit is different

from its original value, 11 ECC parity bits are changed from

the original ECC parity bits. Take the ECC parity from the

hardware ECC engine and perform bit-wise exclusive OR

with it and the ECC parity field in NAND Flash. The result

can be as follows.

All bits are 0. The data is correct.

Eleven bits are 1. One bit error has been detected.

Use the eleven bits to identify the error bit position.

One bit is 1. One bit in ECC field is corrupt. Data area

should be OK.

Otherwise, two or more data bits are corrupt. Cannot

be corrected.

4.18.2 NOR Flash Controller/General Purpose Chip

Select

The NOR Flash Controller supports up to four independent

chip selects that can be used for NOR Flash devices or

General Purpose Chip Selects (GPCS). Up to 28 bits of

address is supported for each chip select, allowing byte-

wide linear arrays up to 256 MB in memory space. Chips

selects may also be located in I/O space, but the usable

address bits are limited by the over all limits of I/O space.

Each chip select is independently programmable:

• Address Setup: Defaults to seven Local bus clocks

• Read/Write Strobe Width: Defaults to seven Local bus

clocks

• Address Hold: Defaults to seven Local bus clocks cycles

• Optional Wait State Insertion: Defaults off, driven by an

external input (FLASH_IOCHRDY) to be used by

General Purpose devices.

• Optional Write Protect: Defaults protected

These settings are located in MSR space and on hard

reset default to the settings listed above. Hence, virtually

any NOR device can be used immediately out of reset for

first instruction fetch. After booting, delays can be pro-

grammed as appropriate.

Table 4-36. ECC Parity and Bit Address Relationship

Parity

Bit Address

Parity

Bit Address

CP0

xxxx_xxxx, xx0

CP1

xxxx_xxxx, xx1

CP2

xxxx_xxxx, x0x

CP3

xxxx_xxxx, x1x

CP4

xxxx_xxxx, 0xx

CP5

xxxx_xxxx, 1xx

LP00

xxxx_xxx0, xxx

LP01

xxxx_xxx1, xxx

LP02

xxxx_xx0x, xxx

LP03

xxxx_xx1x, xxx

LP04

xxxx_x0xx, xxx

LP05

xxxx_x1xx, xxx

LP06

xxxx_0xxx, xxx

LP07

xxxx_1xxx, xxx

LP08

xxx0_xxxx, xxx

LP09

xxx1_xxxx, xxx

LP10

xx0x_xxxx, xxx

LP11

xx1x_xxxx, xxx

LP12

x0xx_xxxx, xxx

LP13

x1xx_xxxx, xxx

LP14

0xxx_xxxx, xxx

LP15

1xxx_xxxx, xxx

CS5535 датащи(PDF) 171 Page - National Semiconductor (TI)

CS5535 датащи(HTML) 171 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL