CS5535 datasheet(376/555 Pages) NSC

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Revision 0.8

UART/IR Controller Register Descriptions (Continued)

5.12.3.5

Modem/Mode Control Register (MCR)

MCR controls the virtual interface with the modem or data communications set in loopback mode, and the device opera-

tional mode when the device is in the extended mode. This register function differs for extended and non-extended modes.

Modem control pins are not available and are replaced with the virtual interface (except RTS and DTR signals) controlled by

software only through MSR_UART[x]_MOD (see Section 5.12.1.1 on page 363).

MCR, Extended Mode (EXCR1.EXT_SL = 1)

In extended mode, this register is used to select the operation mode (IrDA, Sharp, etc.) of the device and enable the DMA

interface. In these modes, the interrupt output signal is always enabled, and loopback can be enabled by setting bit 4 of

EXCR1. Bits 2 to 7 should always be initialized when the operation mode is changed from non-extended to extended.

I/O Offset

04h

Type

R/W

Reset Value

00h

MCR Extended Mode Register Map

MDSL[2:0]

RSVD

TX_DFR

DMA_EN

RTS

DTR

MCR Extended Mode Bit Descriptions

Bit

Name

Description

7:5

MDSL[2:0]

Mode Select [2:0]. These bits select the operation mode of the functional block when in

extended mode. When the mode is changed, the TX_FIFO and RX_FIFOs are flushed,

Link Status and Modem Status Interrupts are cleared, and all of the bits in the Auxiliary

Status and Control register are cleared.

000: UART (Default)

001: Reserved

010: Sharp-IR

011: SIR

100: Reserved

101: Reserved

110: CEIR

111: Reserved

RSVD

Reserved. Write as 0.

3TX_DFR

Transmit Deferral. For a detailed description of the transmit deferral see Section 4.11.1.6

"Transmit Deferral" on page 130. This bit is effective only if the TX_FIFO is enabled (FCR

bit 0 = 1).

0: No transmit deferral enabled. (Default.)

1: Transmit deferral enabled.

2DMA_EN

DMA Enable. When set to1, DMA mode of operation is enabled. When DMA is selected,

transmit and/or receive interrupts should be disabled to avoid spurious interrupts. DMA

cycles always address the Data Holding registers or FIFOs, regardless of the selected

bank.

0: DMA mode disabled. (Default.)

1: DMA mode enabled.

1RTS

Request To Send. When loopback is enabled (bit 4 of EXCR1 = 1, Bank 2, I/O Offset

02h), this bit internally drives both CTS and DCD. Otherwise it is unused.

0DTR

Data Terminal Ready. When loopback is enabled (bit 4 of EXCR1 = 1, Bank 2, I/O Offset

02h), this bit internally drives both DSR and RI. Otherwise it is unused.

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