CS5535 datasheet(359/555 Pages) NSC

359 / 555 page

Revision 0.8

359

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SMB Controller Register Descriptions (Continued)

5.11.1.6

SMB Control 2 (SMB_CTRL2)

This register enables/disables the functional block and determines the SMB clock rate.

5.11.1.7

SMB Control 3 (SMB_CTRL3)

This register enables/disables the functional block and determines the SMB clock rate.

SMB I/O Offset

05h

Type

R/W

Reset Value

00h

SMB_CTRL2 Register Map

SCLFRQ

SMB_CTRL2 Bit Descriptions

Bit

Name

Description

7SCLFRQ

SMB_CLK Frequency. This field along with SMBCTL3 defines the SMB_CLK period

(low and high time) when the device serves as a bus master. The clock low and high

times are defined as follows:

tSCLl = tSCLh = 2*SCLFRQ*tCLK

where tCLK is the module input clock cycle.

SCLFRQ can be programmed to values in the range of 00010002 (810) through

11111112 (12710). Using any other value has unpredictable results.

The low and high time are generally equal unless two or more devices are driving the

SCL line.

6:0

Enable.

0: SMB is disabled, all registers are cleared, and clocks are halted. In the SMBCST

1: SMB is enabled.

SMB I/O Offset

06h

Type

R/W

Reset Value

00h

SMB_CTRL3 Register Map

SCLFRQ

SMB_CTRL3 Bit Descriptions

Bit

Name

Description

7:0

SCLFRQ

SMB_CLK Frequency. This field along with SMBCTL2.SCLFRQ defines the

SMB_CLK period (low and high time) when the device serves as a bus master. The

clock low and high times are defined as follows:

tSCLl = tSCLh = 2*SCLFRQ*tCLK

where tCLK is the module input clock cycle.

The highest value that can be programmed into these two registers for lowest fre-

quency is FFFFh and the lowest value is 0008h.

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