CS5535 datasheet(358/555 Pages) NSC

358 / 555 page

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358

Revision 0.8

SMB Controller Register Descriptions (Continued)

5.11.1.5

SMB Address (SMB_ADDR)

1STOP

Stop.

0: Automatically cleared after Stop issued.

1: Setting this bit in master mode generates a Stop condition to complete or abort cur-

rent message transfer.

0START

Start. Set this bit only when in master mode or when requesting master mode.

0: Cleared after Start condition sent or Bus Error (BER (SMB I/O Offset 01h[5]) = 1)

detected.

1: Single or repeated Start condition generated on the SMB. If the device is not the

active master of the bus (MASTER (SMB I/O Offset 01h[1]) = 0), setting START gen-

erates a Start condition when the SMB becomes free (BB (SMB I/O Offset 02h[1]) =

0). An address transmission sequence should then be performed.

If the device is the active master of the bus (MASTER = 1), setting START and then

writing to SMBSDA generates a Start condition. If a transmission is already in

progress, a repeated Start condition is generated. This condition can be used to

switch the direction of the data flow between the master and the slave, or to choose

another slave device without separating them with a Stop condition.

SMB I/O Offset

04h

Type

R/W

Reset Value

00h

SMB_ADDR Register Map

SAEN

SMBADDR

SMB_ADDR Bit Descriptions

Bit

Name

Description

SAEN

Slave Enable.

0: SMB does not check for an address match with address field.

1: Address field holds a valid address and enables the match of ADDR to an incoming

address byte.

6:0

SMBADDR

Device address (SMB Own Address). These bits hold the 7-bit device address. When

in slave mode, the first 7 bits received after a Start condition are compared with this

field (first bit received is compared with bit 6, and the last bit with bit 0). If the address

field matches the received data and SAEN (bit 7) is 1, a match is declared.

SMB_CTRL1 Bit Descriptions

Bit

Name

Description

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