CS5535 datasheet(319/555 Pages) NSC

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DIVIL Register Descriptions (Continued)

The enables default to 0. If 0, reads or writes to the indicated device are blocked during activity. This may cause an SSMI

or ERROR if enabled by the associated MSR. Thus, writes are discarded and reads return all Fs. If an enable is 0, a chip

select for the indicated device is not asserted. If an enable is 1, the indicated device is available for access during activity.

DIVIL_AC_DMA Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

87654321

RSVD

DIVIL_AC_DMA Bit Descriptions

Bit

Name

Description

31:18

RSVD

Reserved. Reads return 0; writes have no effect.

AC_DMA_W

Allow DMA Writes during DMA Activity. If set, this bit allows writes to the DMA con-

troller during DMA activity (data transfers). This mechanism may be used, among other

things, to abort a hung DMA transfer. If clear, DMA controller writes are locked out dur-

ing DMA activity.

AC_DMA_R

Allow DMA Reads during DMA Activity. If set, this bit allows reads from the DMA

controller during DMA activity (data transfers). If clear, DMA controller reads are locked

out during DMA activity.

15:4

RSVD

Reserved. Reads return 0; writes have no effect.

AC_DMA_LPC_

LPC I/O Writes during LPC DMA If set, this bit allows I/O writes to the LPC bus during

LPC DMA transfer. If clear, I/O writes are locked out during LPC DMA transfers.

AC_DMA_LPC_IR

LPC I/O Reads during LPC DMA. If set, this bit allows I/O reads to the LPC bus during

LPC DMA transfer. If clear, I/O reads are locked out during LPC DMA transfers.

AC_DMA_LPC_

LPC Memory Writes during LPC DMA. If set, this bit allows memory writes to the LPC

bus during LPC DMA transfer. If clear, memory writes are locked out during LPC DMA

transfers.

AC_DMA_LPC_

LPC Memory Reads during LPC DMA. If set, this bit allows memory reads to the LPC

bus during LPC DMA transfer. If clear, memory reads are locked out during LPC DMA

transfers.

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