CS5535 datasheet(315/555 Pages) NSC

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DIVIL Register Descriptions (Continued)

5.6.2.10

Legacy I/O Space Controls (DIVIL_LEG_IO)

MSR Address

51400014h

Type

R/W

Reset Value

04000003h

DIVIL_LEG_IO Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

87654321

RSVD

DIVIL_LEG_IO Bit Description

Bit

Name

Description

RESET_SHUT_

Shutdown Reset Enable If set, this bit will enable the issuance of the RESET_OUT#

signal upon the detection of a PCI Shutdown cycle from the GX2 (or any other PCI

master). The reason for the reset is recorded in the PM_SSC register (PMS I/O Offset

54h[9], see Section 5.18.3.19 on page 499 for bit details).

0: Do not issue RESET_OUT# upon detection of Shutdown cycle.

1: Issue RESET_OUT# upon detection of Shutdown cycle.

RESET_BAD_EN

Bad Transaction Reset Enable If set, this bit will enable a system wide reset via the

RESET_OUT# signal, if the GeodeLink Adapter detects a ‘bad’ GeodeLink transaction.

The reason for the reset is recorded in the PM_SSC register (PMS I/O Offset 54h[12],

see Section 5.18.3.19 on page 499 for bit details).

0: Do not issue RESET_OUT# upon detection of a “bad” transaction.

1: Issue RESET_OUT# upon detection of a “bad” transaction

RSVD

Reserved: This bit should always be written to 0.

SPEC_CYC_MD

Special Cycle Mode. Allows selection of how the DIVIL decodes Local bus address for

GeodeLink special cycles. (Defaults 0.)

0: Decode is per the PCI spec:

00h: Shutdown.

01h: Halt.

All other values ignored.

1: Decode is per the x86 standard:

00h: Shutdown.

02h: Halt.

All other values ignored.

0X000E_XXXX

000Exxxxh Remap. If high, memory addresses in the range of 000Exxxxh are re-

mapped to FFFExxxxh. Applies to addresses except the LBAR comparators and other

address decode functions. (Defaults 0.)

0X000F_XXXX

000Fxxxxh Remap. If high, memory addresses in the range of 000Fxxxxh are re-

mapped to FFFFxxxxh. Applies to addresses except the LBAR comparators and other

address decode functions. (Defaults 1.)

LPC_DISABLE_

MEM

LPC Disable Memory. If high, discard all memory writes which would otherwise go to

the LPC by default. For reads, return all 1s. “Default” means any address not explicitly

mapped into on-chip memory space or claimed by an LBAR hit.

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