CS5535 datasheet(225/555 Pages) NSC

225 / 555 page

Revision 0.8

225

www.national.com

GLPCI_SB Register Descriptions (Continued)

5.2.3

PCI Configuration Registers

The first 16 bytes of the PCI configuration register space

consist of standard PCI header registers. An additional 32

bytes are used to implement a mailbox for giving access

from the PCI bus to the internal MSRs of the CS5535.

MSR Access Mailbox

Upon reset, MSR access is enabled. That is, the PMC-

TRL.EN bit is set. A PCI configuration (config) write to reg-

ister F0h clearing the EN bit is required to disable MSR

access.

An MSR read is accomplished by:

• A PCI configuration write to register F4h (PMADDR)

with the appropriate address value. If the appropriate

address value was previously written to register F4h,

then this step is unnecessary.

• A PCI configuration read of register F8h (PMDATA0).

This starts the GLIU MSR read. The PCI bus is held

(i.e., no retry unless time-out) until the transaction

completes.

• A PCI configuration read of register FCh (PMDATA1).

The PCI bus is held (i.e., no retry unless time-out) until

the transaction completes.

An MSR write is accomplished by:

• A PCI configuration write to register F4h (PMADDR)

with the appropriate address value. If the appropriate

address value was previously written to register F4h,

then this step is unnecessary.

• A PCI configuration write to register F8h (PMDATA0).

• A PCI configuration write to register FCh (PMDATA1).

This starts the GLIU MSR write. The PCI bus is held

(i.e., no retry unless time-out) until the transaction

completes.

Any PCI transaction interrupting an MSR read/write trans-

action is retried until the MSR transaction is complete.

The

external

MSR

write

request

always

has

the

SEND_RESPONSE bit set. The returned MSR read or

write response packet is checked for the SSMI and EXCEP

bits.

5.2.3.1

PCI Configuration Space Header Byte 0-3 (GLPCI_PCI_HEAD_BYTE0-3)

PCI Index

00h

Type

Reset Value

002A100Bh

GLPCI_PCI_HEAD_BYTE0-3 Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

7654321

DEV_ID

VEN_ID

GLPCI_PCI_HEAD_BYTE0-3 Bit Descriptions

Bit

Name

Description

31:16

DEV_ID

Device Identification Register (Read Only). Identifies CS5535 as the device. Reads as

002Ah.

15:0

VEN_ID

Vendor Identification Register (Read Only). Identifies National Semiconductor as the

vendor. Reads as 100Bh.

CS5535 датащи(PDF) 225 Page - National Semiconductor (TI)

CS5535 датащи(HTML) 225 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL