WM8985GEFLSLASHR datasheet(94/118 Pages) WOLFSON

94 / 118 page

WM8985

Pre-Production

PP, Rev 3.4, October 2006

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

4:2

BCLKDIV

000

Configures the BCLK output frequency, for use

when the chip is master over BCLK.

000=divide by 1 (BCLK=MCLK)

001=divide by 2 (BCLK=MCLK/2)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

Digital Audio

Interfaces

Reserved. Initialise to 0

Sets the chip to be master over LRC and BCLK

0=BCLK and LRC clock are inputs

1=BCLK and LRC clock are outputs generated

by the WM8978 (MASTER)

Digital Audio

Interfaces

M128ENB

0 = low power mode enabled

1 = low power mode disabled

Additional

Control

7:4

DCLKDIV

1000

Controls clock division from SYSCLK to

generate suitable class D clock.

Recommended class D clock frequency =

1.4MHz.

0000 = divide by 1

0010 = divide by 2

0011 = divide by 3

0100 = divide by 4

0101 = divide by 5.5

0110 = divide by 6

1000 = divide by 8

1001 = divide by 12

1010 = divide by 16

Class A / D

Headphone

Outputs

3:1

000

Approximate sample rate (configures the

coefficients for the internal digital filters):

000=48kHz

001=32kHz

010=24kHz

011=16kHz

100=12kHz

101=8kHz

110-111=reserved

Audio Sample

Rates

7 (07h)

SLOWCLKEN

Slow clock enable. Used for both the jack insert

detect debounce circuit and the zero cross

timeout.

0 = slow clock disabled

1 = slow clock enabled

Analogue

Outputs

GPIO1GP

GPIO1 Open drain enable

0 = Open drain disabled

1 = Open drain enabled

General

Purpose

Input/Output

(GPIO)

GPIO1GPU

GPIO1 Internal pull-up enable:

0 = Internal pull-up disabled

1 = Internal pull-up enabled

General

Purpose

Input/Output

(GPIO)

8 (08h)

GPIO1GPD

GPIO1 Internal pull-down enable:

0 = Internal pull-down disabled

1 = Internal pull-down enabled

General

Purpose

Input/Output

(GPIO)

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