AD5371BBCZ datasheet(19/25 Pages) AD

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Preliminary Technical Data

AD5371

Rev. P

rF | Page 19 of 25

SPI READBACK MODE

The AD5371 allows data readback via the serial interface from

every register directly accessible to the serial interface, which is

all registers except the X2A, X2B and DAC registers. In order to

read back a register, it is first necessary to tell the AD5371

which register is to be read. This is achieved by writing to the

device a word whose first two bits are the special function code

00. The remaining bits then determine if the operation is a

readback, and the register which is to be read back, or if it is a

write to of the special function registers such as the control

After the special function write has been performed, if it is a

readback command then data from the selected register will be

clocked out of the SDO pin during the next SPI operation. The

SDO pin is normally three-state but becomes driven as soon as

a read command has been issued. The pin will remain driven

until the registers data has been clocked out. Figure 5 for the

read timing diagram. Note that due to the timing requirements

of t5 (25ns) the maximum speed of the SPI interface during a

read operation should not exceed 20MHz.

LVDS OPERATION

The LVDS interface operates as follows (note that, since the

LVDS signals are differential, when a signal goes high its

complementary signal goes low, and vice versa).

The SYNC signal frames the data. SCLK is initially high. After

SYNC goes low and the SYNC to SCLK setup time has elapsed,

SCLK can start to clock in the data. Data is clocked into the

AD5371 on the high to low transition of SCLK and must be

stable at this time (observe setup and hold time specs). SYNC

may then be taken high after the SCLK to SYNC hold time to

latch the data.

The same comments about burst and continuous clocks apply

to the LVDS interface as to the SPI interface. Readback is not

available when using the LVDS interface.

As mentioned previously the value of the X2 (A or B) register is

calculated each time the user writes new data to the

corresponding X1, C or M registers. The calculation is

performed by a three stage process. The first two stages take

500ns each and the third stage takes 250ns. When the write to

one of the X1, C or M registers is complete the calculation

process begins. If the write operation involves the update of a

single DAC channel the user is free to write to another register

provided that the write operation doesn’t finish until the first

stage calculation is complete, i.e. 500ns after the completion of

the first write operation. If a group of channels is being updated

by a single write operation the first stage calculation will be

repeated for each channel, taking 500ns per channel. In this

case the user should not complete the next write operation until

this time has elapsed.

CHANNEL ADDRESSING AND SPECIAL MODES

If the mode bits are not 00, then the data word D13 to D0 is

written to the device. Address bits A5 to A0 determine which

channel or channels is/are written to, while the mode bits

determine to which register (X1A, X1B, C or M) the data is

written, as shown in Table 8. If data is to be written to the X1A

or X1B register, the setting of the A/B bit in the Control

X1A, 1

X1B).

Table 9. Mode Bits

Action

Write DAC input data (X1A or X1B) register,

depending on Control Register A/B bit.

Write DAC offset (C) register

Write DAC gain (M) register

Special function, used in combination with other

bits of word

The AD5371 has very flexible addressing that allows writing of

data to a single channel, all channels in a group, the same

channel in groups 0 to 4 or groups 1 to 4, or all channels in the

device Table 10 shows all these address modes.

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