Preliminary Technical Data

AD5371

Rev. P

rF | Page 18 of 25

SERIAL INTERFACE

The AD5371 contains two high-speed serial interfaces, an SPI-

compatible, interface operating at clock frequencies up to

50MHz (20MHz for read operations), and an LVDS interface.

To minimize both the power consumption of the device and

on-chip digital noise, the interface powers up fully only when

the device is being written to, that is, on the falling edge of

SYNC.

SPI INTERFACE

The serial interface is 2.5 V LVTTL compatible when operating

when the SPI/LVDS pin is held low.It is controlled by four pins,

as follows.

SYNC

Frame synchronization input.

SDI

Serial data input pin.

SCLK

Clocks data in and out of the device.

SDO

Serial data output pin for data readback.

When the SPI mode is used the SYNC, SDI and SCLK pins

should be connected to DGND either directly or by using pull-

down resistors.

LVDS INTERFACE

The LVDS interface is selected when the SPI/LVDS pin is held

high. The LVDS interface uses the same input pins as the SPI

interface with the same designations. SDO is not used. In

addition, three other pins are provided for the complementary

signals needed for differential operation, thus:

SYNC/SYNC

Differential frame synchronization signal.

SDI/SDI

Differential serial data input.

SCLK/SCLK

SPI WRITE MODE

The AD5371 allows writing of data via the serial interface to

every register directly accessible to the serial interface, which is

all registers except the X2A and X2B registers and the DAC

registers. The X2A and X2B registers are updated when writing

to the X1A, X1B, M and C registers, and the DAC registers are

updated by LDAC.

The serial word (see Table 8) is 24 bits long. 14 of these bits are

data bits, six bits are address bits, and two bits are mode bits

that determine what is done with the data. Two bits are

reserved.

The serial interface works with both a continuous and a burst

(gated) serial clock. Serial data applied to SDI is clocked into the

AD5371 by clock pulses applied to SCLK. The first falling edge

of SYNC starts the write cycle. At least 24 falling clock edges

must be applied to SCLK to clock in 24 bits of data, before

SYNC is taken high again. If SYNC is taken high before the

24th falling clock edge, the write operation will be aborted.

If a continuous clock is used, SYNC must be taken high before

the 25th falling clock edge. This inhibits the clock within the

AD5371. If more than 24 falling clock edges are applied before

SYNC is taken high again, the input data will be corrupted. If an

externally gated clock of exactly 24 pulses is used, SYNC may be

taken high any time after the 24th falling clock edge.

The input register addressed is updated on the rising edge of

SYNC. In order for another serial transfer to take place, SYNC

must be taken low again.

Differential clock input.

Table 8. Serial Word Bit Assignation

I23

I22

I21

I20

I19

I18

I17

I16

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1*

I0*

M1

M0

A5

A4

A3

A2

A1

A0

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

*Bits I1 and I0 are reserved for future use. Set to 0 when writing. Read back as 0.