AD5371BBCZ datasheet(16/25 Pages) AD

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Preliminary Technical Data

AD5371

Rev. P

rF | Page 16 of 25

Offset Error = ±70mV

=> Maximum Offset Error Span = 2(70mV)=0.14V

=> Output Range including Gain Error and Offset Error =

12.36V + 0.14V = 12.5V

VREF Calculation

Actual Output Range = 12.5V, that is -4.25V to +8.25V

(centered);

VREF = (8.25V + 4.25V)/4 = 3.125V

If the solution yields an inconvenient reference level, the user

can adopt one of the following approaches:

Use a resistor divider to divide down a convenient,

higher reference level to the required level.

Select a convenient reference level above VREF and

modify the Gain and Offset registers to digitally

downsize the reference. In this way the user can use

almost any convenient reference level but may reduce

the performance by overcompaction of the transfer

function.

Use a combination of these two approaches

CALIBRATION

The user can perform a system calibration on the AD5371 to

reduce gain and offset errors to below 1 LSB. This is achieved by

calculating new values for the m and c registers and

reprogramming them.

Reducing Offset and Gain Error

Offset Error is reduced as follows:

1. Set the output to the lowest possible value.

2. Measure the actual output voltage and compare it to the

required value. This gives the offset error.

3. Calculate the number of LSBs equivalent to the offset error

and add or subtract this from the default value of the c register.

Gain Error is reduced as follows:

1. Reduce the offset error.

2. Set the output to the highest possible value

3. Measure the actual output voltage and compare it to the

required value. This gives the gain error.

4. Calculate the number of LSBs equivalent to the gain error

and subtract it from the default value of the m register. Note

that only positive gain error can be reduced.

CALIBRATION EXAMPLE

This example assumes that a -4V to +8V output is required. The

DAC output is set to -4V but is measured at -4.03V. This gives

an offset of

-30mV.

1 LSB = 12V/16384 = 732.42µV

30mV = 41 LSBs

41 LSBs should be added to the default c register value:

(8192 + 41) = 8151

8151 should be programmed to the c register

The gain error can now be removed. The output is set to +8V

and a value of +8.02V is measured. This is a gain error of

+20mV

20mV = 27 LSBs

27 LSBs should be subtracted from the default m register

value: (16383-27) = 16356.

16356 should be programmed to the m register

RESET FUNCTION

When the RESET pin is taken low, the DAC buffers are

disconnected and the DAC outputs VOUT0 to VOUT39 are

tied to their associated SIGGND signals via a 10 kΩ resistor. On

the rising edge of RESET the AD5371 state machine initiates a

reset sequence to reset the X, M and C registers to their default

values. This sequence typically takes 300µs and the user should

not write to the part during this time. When the reset sequence

is complete, and provided that CLR is high, the DAC output will

be at a potential specified by the default register settings which

will be equivalent to SIGGGND. The DAC outputs will remain

at SIGGND until the X, M or C registers are updated and LDAC

is taken low.

CLEAR FUNCTION

CLR is an active low input which should be high for normal

operation. The CLR pin has in internal 500kΩ pull-down

resistor. When CLR is low, the input to each of the DAC output

buffer stages, VOUT0 to VOUT39, is switched to the externally

set potential on the relevant SIGGND pin. While CLR is low, all

LDAC pulses are ignored. When CLR is taken high again, the

DAC outputs remain cleared until LDAC is taken low. The

contents of input registers and DAC registers 0 to 39 are not

affected by taking CLR low. To prevent glitches appearing on

the outputs CLR should be brought low whenever the output

span is adjusted by writing to the offset DAC.

BUSY AND LDAC FUNCTIONS

The value of an X2 (A or B) register is calculated each time the

user writes new data to the corresponding X1, C, or M registers.

During the calculation of X2, the BUSY output goes low. While

BUSY is low, the user can continue writing new data to the X1,

M, or C registers (see the Register Update Rates section for

more details), but no DAC output updates can take place. The

DAC outputs are updated by taking the LDAC input low. If

LDAC goes low while BUSY is active, the LDAC event is stored

and the DAC outputs update immediately after BUSY goes

high. A user can also hold the LDAC input permanently low. In

this case, the DAC outputs update immediately after BUSY

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