ST7789V2 datasheet(9/319 Pages) SITRONIX

9 / 319 page

ST7789V2

Version 1.0

Page 9 of 319

2016/11

Sitronix Confidential

The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or

disclosed in whole or in part without prior written permission of Sitronix.

LIST OF FIGURES

FIGURE 1 PARALLEL INTERFACE TIMING CHARACTERISTICS (8080-SERIES MCU INTERFACE)................................. 41

FIGURE 2 RISING AND FALLING TIMING FOR I/O SIGNAL .............................................................................................. 42

FIGURE 3 WRITE-TO-READ AND READ-TO-WRITE TIMING........................................................................................... 42

FIGURE 4 3-LINE SERIAL INTERFACE TIMING CHARACTERISTICS................................................................................. 43

FIGURE 5 4-LINE SERIAL INTERFACE TIMING CHARACTERISTICS................................................................................. 44

FIGURE 6 RGB INTERFACE TIMING CHARACTERISTICS................................................................................................ 46

FIGURE 7 RESET TIMING ................................................................................................................................................. 48

FIGURE 8 8080-SERIES WRX PROTOCOL....................................................................................................................... 52

FIGURE 9 8080-SERIES PARALLEL BUS PROTOCOL, WRITE TO REGISTER OR DISPLAY RAM .................................... 52

FIGURE 10 8080-SERIES RDX PROTOCOL....................................................................................................................... 53

FIGURE 11 8080-SERIES PARALLEL BUS PROTOCOL, READ DATA FROM REGISTER OR DISPLAY RAM .......................... 53

FIGURE 12 SERIAL INTERFACE DATA STREAM FORMAT .................................................................................................. 56

FIGURE 13 3-LINE SERIAL INTERFACE WRITE PROTOCOL (WRITE TO REGISTER WITH CONTROL BIT IN TRANSMISSION)

................................................................................................................................................................................. 57

FIGURE 14 4-LINE SERIAL INTERFACE WRITE PROTOCOL (WRITE TO REGISTER WITH CONTROL BIT IN TRANSMISSION)

................................................................................................................................................................................. 57

FIGURE 15 3-LINE SERIAL INTERFACE READ PROTOCOL ................................................................................................ 59

FIGURE 16 4-LINE SERIAL INTERFACE READ PROTOCOL ................................................................................................ 61

FIGURE 17 HARDWARE SUGGESTION OF 2 DATA LANE SERIAL INTERFACE .................................................................... 62

FIGURE 18 3-LINE SERIAL INTERFACE WRITE PROTOCOL (WRITE TO REGISTER WITH CONTROL BIT IN TRANSMISSION)

................................................................................................................................................................................. 63

FIGURE 19 3-LINE SERIAL INTERFACE READ PROTOCOL ................................................................................................ 65

FIGURE 20 WRITE INTERRUPTS RECOVERY (SERIAL INTERFACE).................................................................................. 66

FIGURE 21 WRITE INTERRUPTS RECOVERY (BOTH SERIAL AND PARALLEL INTERFACE) .............................................. 67

FIGURE 22 PARALLEL BUS PAUSE PROTOCOL (PAUSED BY CSX) .................................................................................... 68

FIGURE 23 RGB INTERFACE DATA FORMAT................................................................................................................. 114

FIGURE 24 DRAM ACCESS AREA BY RGB INTERFACE................................................................................................ 115

FIGURE 25 TIMING CHART OF SIGNALS IN RGB INTERFACE DE MODE ..................................................................... 117

FIGURE 26 TIMING CHART OF RGB INTERFACE HV MOD............................................................................................ 118

FIGURE 27 DATA TRANSMISSION THROUGH VSYNC INTERFACE ................................................................................ 120

FIGURE 28 OPERATION THROUGH VSYNC INTERFACE............................................................................................... 120

FIGURE 29 TIMING DIAGRAM OF VSYNC INTERFACE................................................................................................. 121

FIGURE 30 OPERATION FOR LEADING MODE OF VSYNC INTERFACE ........................................................................ 122

FIGURE 31 OPERATION FOR LAGGING MODE OF VSYNC INTERFACE........................................................................ 122

FIGURE 32 DISPLAY DATA RAM ORGANIZATION .......................................................................................................... 124

FIGURE 33 DISPLAY DATA RAM ORGANIZATION .......................................................................................................... 127

FIGURE 34 ROLLING SCROLL DEFINITION ................................................................................................................... 130

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