ST7789V2 datasheet(63/319 Pages) SITRONIX

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ST7789V2

Version 1.0

Page 63 of 319

2016/11

Sitronix Confidential

The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or

disclosed in whole or in part without prior written permission of Sitronix.

Command write mode:

The command write protocol of 2-wire data lane serial interface is the same with the 3-line serial interface,

so users can ignore the input data of WRX.

Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is

initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX

enables the serial interface and indicates the start of data transmission.

Figure 18 3-line serial interface write protocol (write to register with control bit in transmission)

SRAM write mode:

The SRAM write mode of 2-wire data line serial interface need use SDA pin and WRX pin to be data input

pins.

Read function:

The read mode of 2-wire data lane serial interface is the same with the 3-line serial interface and WRX

pin can be ignored. To achieve read function, the micro controller first has to send a command (read ID or

required to go to high before a new command is send (see the below figure). The driver samples the SDA

(input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of SCL. Thus the micro

controller is supported to read at the rising edge of SCL.

After the read status command has been sent, the SDA line must be set to tri-state no later than at the

falling edge of SCL of the last bit.

3-line serial interface Ⅰ

Ⅰ

Ⅰ/Ⅱ

Ⅱ

Ⅱ protocol:

3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):

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