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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7789V2 датащи(PDF) 44 Page - Sitronix Technology Co., Ltd. |
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ST7789V2 датащи(HTML) 44 Page - Sitronix Technology Co., Ltd. |
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44 / 319 page  ST7789V2 Version 1.0 Page 44 of 319 2016/11 Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix. 7.4.3 Serial Interface Characteristics (4-line serial): Figure 5 4-line serial Interface Timing Characteristics VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=25 ℃ Signal Symbol Parameter MIN MAX Unit Description CSX TCSS Chip select setup time (write) 15 ns TCSH Chip select hold time (write) 15 ns TCSS Chip select setup time (read) 60 ns TSCC Chip select hold time (read) 65 ns TCHW Chip select “H” pulse width 40 ns SCL TSCYCW Serial clock cycle (Write) 16 ns -write command & data ram TSHW SCL “H” pulse width (Write) 7 ns TSLW SCL “L” pulse width (Write) 7 ns TSCYCR Serial clock cycle (Read) 150 ns -read command & data ram TSHR SCL “H” pulse width (Read) 60 ns TSLR SCL “L” pulse width (Read) 60 ns D/CX TDCS D/CX setup time 10 ns TDCH D/CX hold time 10 ns SDA (DIN) TSDS Data setup time 7 ns TSDH Data hold time 7 ns DOUT TACC Access time 10 50 ns For maximum CL=30pF For minimum CL=8pF TOH Output disable time 15 50 ns Table 6 4-line serial Interface Characteristics Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as |
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