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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7789V2 датащи(PDF) 48 Page - Sitronix Technology Co., Ltd. |
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ST7789V2 датащи(HTML) 48 Page - Sitronix Technology Co., Ltd. |
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48 / 319 page  ST7789V2 Version 1.0 Page 48 of 319 2016/11 Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix. 7.4.5 Reset Timing: Display status T RW T RT During reset Initial condition (Default for H/W reset) RESX Normal operation Shorter than 5us Figure 7 Reset Timing VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=25 ℃ Related Pins Symbol Parameter MIN MAX Unit RESX TRW Reset pulse duration 10 - us TRT Reset cancel - 5 (Note 1, 5) ms 120 (Note 1, 6, 7) ms Table 9 Reset Timing Notes: 1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from NVM (or similar device) to registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a rising edge of RESX. 2. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below: RESX Pulse Action Shorter than 5us Reset Rejected Longer than 9us Reset Between 5us and 9us Reset starts 3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode.) and then return to Default condition for Hardware Reset. 4. Spike Rejection also applies during a valid reset pulse as shown below: |
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