SLG47502V datasheet(2/192 Pages) RENESAS

2 / 192 page

Datasheet

28-Feb-2023

CFR0011-120-00

Revision 2.3

2 of 194

SLG47512/13

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

Contents

General Description ................................................................................................................................................................. 1

Key Features............................................................................................................................................................................. 1

Applications.............................................................................................................................................................................. 1

1 Block Diagram ...................................................................................................................................................................... 7

2 Pinout .................................................................................................................................................................................... 8

2.1 Pin Configuration - STQFN- 12L ............................................................................................................................ 8

2.2 Pin Configuration - MSTQFN- 16L ......................................................................................................................... 9

3 Characteristics ...................................................................................................................................................................13

3.1 Absolute Maximum Ratings .................................................................................................................................13

3.2 Electrostatic Discharge Ratings ...........................................................................................................................13

3.3 Recommended Operating Conditions .................................................................................................................13

3.4 Electrical Characteristics ......................................................................................................................................14

3.5 I2C Pins Electrical Characteristics ........................................................................................................................16

3.6 Macrocells Current Consumption .........................................................................................................................19

3.7 Timing Characteristics ..........................................................................................................................................19

3.8 Counter/Delay Characteristics .............................................................................................................................22

3.9 Oscillator Characteristics .....................................................................................................................................23

3.10 ACMP Characteristics ........................................................................................................................................23

3.11 Analog Temperature Sensor Characteristics .....................................................................................................25

4 User Programmability ........................................................................................................................................................26

5 IO Pins .................................................................................................................................................................................27

5.1 GPIO Pins ............................................................................................................................................................27

5.2 GPI Pin .................................................................................................................................................................27

5.3 Pull-Up/Down Resistors .......................................................................................................................................27

5.4 Fast Pull-up/down during Power-up .....................................................................................................................27

5.5 GPI Structure .......................................................................................................................................................28

5.6 GPIO with I2C Mode IO Structure ........................................................................................................................29

5.7 Matrix OE IO Structure .........................................................................................................................................30

5.8 IO Typical Performance .......................................................................................................................................31

6 Connection Matrix ..............................................................................................................................................................34

6.1 Matrix Input Table ...............................................................................................................................................35

6.2 Matrix Output Table ..............................................................................................................................................37

6.3 Connection Matrix Virtual Inputs ..........................................................................................................................40

7 Combination Function Macrocells ....................................................................................................................................41

7.1 2-Bit LUT or D Flip-Flop or Shift Register Macrocells ..........................................................................................41

7.2 2-bit LUT or Programmable Pattern Generator ....................................................................................................46

7.3 3-Bit LUT or D Flip-Flop with Set/Reset or Shift Register Macrocells ..................................................................48

7.4 4-Bit LUT or D Flip-Flop with Set/Reset or Shift Register Macrocell ....................................................................60

8 Multi-Function Macrocells .................................................................................................................................................64

8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells ..............................................................................64

8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell ..............................................................................73

8.3 CNT/DLY Timing Diagrams ..................................................................................................................................76

8.4 FSM Timing Diagrams .........................................................................................................................................83

8.5 Wake and Sleep Controller ..................................................................................................................................86

9 Analog Comparators ..........................................................................................................................................................91

9.1 ACMP0H Block Diagram ......................................................................................................................................92

9.2 ACMP1H Block Diagram ......................................................................................................................................93

9.3 ACMP Typical Performance .................................................................................................................................94

10 Programmable Delay/Edge Detector ..............................................................................................................................95

10.1 Programmable Delay Timing Diagram - Edge Detector Output .........................................................................95

11 Additional Logic Function. Deglitch Filter .....................................................................................................................96

12 Voltage Reference ............................................................................................................................................................97

12.1 Voltage Reference Overview .............................................................................................................................97

12.2 Vref Selection Table ...........................................................................................................................................97

12.3 Vref Block Diagram ...........................................................................................................................................98

SLG47502V датащи(PDF) 2 Page - Renesas Technology Corp

SLG47502V датащи(HTML) 2 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL