SLG47502V datasheet(38/192 Pages) RENESAS

38 / 192 page

Datasheet

28-Feb-2023

CFR0011-120-00

Revision 2.3

38 of 194

SLG47512/13

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

[261:256]

IN1 of LUT3_9 or Data Input of DFF12 or Data Input of Shift_Reg12

[267:262]

IN2 of LUT3_9 or nRST(nSET) of DFF12 or nRST(nSET) of Shift_Reg12

[273:268]

IN0 of LUT4_0 or Clock Input of DFF13 or Clock Input of Shift_Reg13

[279:274]

IN1 of LUT4_0 or Data Input of DFF13 or Data Input of Shift_Reg13

[285:280]

IN2 of LUT4_0 or nRST(nSET) of DFF13 or nRST(nSET) of Shift_Reg13

[291:286]

IN3 of LUT4_0 or Clock Enable of DFF13 or Clock Enable of Shift_Reg13

[297:292]

IN0 of MLT0_LUT4_1 or Clock Input of DFF14 or

Delay0 Input (or Counter0 nRST Input)

[303:298]

IN1 of MLT0_LUT4_1 or nRST (nSET) of DFF14 or

Delay0 Input (or Counter0 nRST Input or External Clock Source)

[309:304]

IN2 of MLT0_LUT4_1 or Data Input of DFF14 or

Delay0 Input (or Counter0 nRST Input)

[315:310]

IN3 of MLT0_LUT4_1

[321:316]

IN0 of MLT1_LUT3_10 or Clock Input of DFF15 or

Delay1 Input (or Counter1 nRST Input)

[327:322]

IN1 of MLT1_LUT3_10 or nRST (nSET) of DFF15 or

Delay1 Input (or Counter1 nRST Input or External Clock Source)

[333:328]

IN2 of MLT1_LUT3_10 or Data Input of DFF15 or

Delay1 Input (or Counter1 nRST Input)

[339:334]

IN0 of MLT2_LUT3_11 or Clock Input of DFF16 or

Delay2 Input (or Counter2 nRST Input)

[345:340]

IN1 of MLT2_LUT3_11 or nRST (nSET) of DFF16 or

Delay2 Input (or Counter2 nRST Input or External Clock Source)

[351:346]

IN2 of MLT2_LUT3_11 or Data Input of DFF16 or

Delay2 Input (or Counter2 nRST Input)

[357:352]

IN0 of MLT3_LUT3_12 or Clock Input of DFF17 or

Delay3 Input (or Counter3 nRST Input)

[363:358]

IN1 of MLT3_LUT3_12 or nRST (nSET) of DFF17 or

Delay3 Input (or Counter3 nRST Input or External Clock Source)

[369:364]

IN2 of MLT3_LUT3_12 or Data Input of DFF17 or

Delay3 Input (or Counter3 nRST Input)

[375:370]

IN0 of MLT4_LUT3_13 or Clock Input of DFF18 or

Delay4 Input (or Counter4 nRST Input)

[381:376]

IN1 of MLT4_LUT3_13 or nRST (nSET) of DFF18 or

Delay4 Input (or Counter4 nRST Input or External Clock Source)

[387:382]

IN2 of MLT4_LUT3_13 or Data Input of DFF18 or

Delay4 Input (or Counter4 nRST Input)

[393:388]

IN0 of MLT5_LUT3_14 or Clock Input of DFF19 or

Delay5 Input (or Counter5 nRST Input)

[399:394]

IN1 of MLT5_LUT3_14 or nRST (nSET) of DFF19 or

Delay5 Input (or Counter5 nRST Input or External Clock Source)

[405:400]

IN2 of MLT5_LUT3_14 or Data Input of DFF19 or

Delay5 Input (or Counter5 nRST Input)

Table 21: Matrix Output Table (Continued)

Address

Matrix Output Signal Function

Matrix Output

Number

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