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CS5308

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cores is relatively constant versus DC current, AC flux

density and frequency. Less expensive core materials (such

as the −52 from Micrometals) change their characteristics

versus DC current, AC flux density, and frequency. The less

expensive materials may yield acceptable converter

performance if the current sense time constant is set

approximately 2× longer than anticipated. For example, use

approximately twice the resistance (RCSn) or twice the

capacitance (CCSn) when using the less expensive core

material. If we use −52 material for this design, the value of

RCSn should be increased to 2 × 50 kW or 100 kW.

8. Error Amplifier Tuning

The error amplifier is tuned by adjusting CAMP to provide

an acceptable full−load transient response as shown in

Figures 22−24. After a value for CAMP is chosen, the

peak−to−peak voltage ripple on the COMP pin is examined

under full−load to insure less than 20 mVPP as shown in

Figure 25.

9. Current Limit Setting

The maximum inductor resistance, the maximum PCB

resistance, and the maximum current−sense gain as shown

in Equation 34 determine the current limit. The maximum

current, IOUT,LIM, was specified in the design requirements.

The maximum inductor resistance occurs at full−load and

the highest ambient temperature. This value was found in the

“Output Inductor Section” (1.58 m

W). The PCB resistance

increases due to the change in ambient temperature:

RPCB,MAX + 0.75 mW @ (1 ) 0.39% °C @ (60 * 25)°C)

+ 0.85 mW

VILIM + (IOUT,LIM ) DILo 2) @ (RLMAX ) RPCB,MAX)

@ GILIM

+ (33 A ) 4.0 A 2) @ (1.29 mW ) 0.85 mW)

@ 6.5 V V

+ 0.486 Vdc

Set the voltage at the ILIM pin using a resistor divider from

the 3.3 V reference output as shown in Figure 27. If the

resistor from ILIM to GND is chosen as 1 k (RLIM2), the

resistor from ILIM to 3.3 V can be calculated from:

RLIM1 + (VREF * VILIM) (VILIM RLIM2)

+ (3.3 V * 0.486 V) (0.486 V 1kW)

+ 5790W or 5.76 kW

RLIM2

1 k

RLIM1

3.3 VREF

To ILIM Pin

VLIM

Figure 27. Setting the Current Limit

10. PWM Comparator Input Voltage

Use Equation 35 to check the voltage level to the positive

pin of the internal PWM comparators to insure the design

will not saturate the comparator at maximum DAC output

voltage with 1% error, AVP at full−load, 100% duty cycle (D

= 1), and maximum internal ramp (310 mV at 100%

duty−cycle):

VCSREF,MAX + Max VID Setting w AVP @ Full−Load

+ 1.01 @ 1.825 V * 45 mV + 1.80 V

VCOn,MAX

+ (IO,MAX 2 ) DILo 2) @ RMAX @ GCSA,MAX

+ (28 A 2 ) 4.0 A 2) @ (1.29 mW ) 0.82 mW)

@ 3.95 V V

+ 0.133 V

VCSREF,MAX ) VCOn,MAX ) 310 mV @ D

+ 1.80 V ) 0.133 V ) 310 mV

+ 2.243 V

(35)

This value is acceptable because it is below the specified

maximum of 2.45 V.

11. VTTPGD Delay Time Setting

To obtain the 335 kHz switching frequency the value of

ROSC was set to 39 kW in Section 6. Figure 4 must be used

to determine the value of the VTTCT Charge Current at this

ROSC value. In this example, the 39 kW ROSC resistor results

in a VTTCT Charge Current of approximately 26 mA. Using

Equation 34 and solving for CVTT:

TD,VTT + (1 V * 0.25 V) @ CVTT VTTCT_Current (34)

CVTT + TD,VTT @ VTTCT_Current 0.75 V

+ 2.5 ms @ 26 mA 0.75 V

+ 0.086 mFor0.1 mF

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