CS5308 datasheet(16/31 Pages) ONSEMI

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CS5308

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Soft Start Enable, and Hiccup Mode

A capacitor between the COMP pin and GND controls

Soft Start and hiccup mode slopes. A 0.1

mF capacitor with

the 30

mA charge current will allow the output to ramp up at

0.3 V/ms or 1.5 V in 5 ms at start−up.

When a fault is detected due to an overcurrent condition

the converter will enter a low duty cycle hiccup mode.

During hiccup mode the converter will not switch from the

time a fault is detected until the Soft Start capacitor has

discharged below the Soft Start Discharge Threshold and

then charged back up above the Channel Start Up Offset.

The COMP pin will disable the converter when pulled

below 0.27 V

VTT Monitoring & VTT Power Good (VTTPGD)

The CS5308 includes VTT monitoring, delay timing and

an open−collector VTT Power Good (VTTPGD) output. A

comparator with a threshold of approximately 1.05 V

monitors VTT. At power−up, VTTPGD is held low and is

released a short time after VTT crosses the 1.05 V threshold.

The time between VTT stabilizing and the release of

VTTPGD is set by a capacitor (CVTT) at the open−collector

VTTCT pin. The voltage at the VTTCT pin will ramp from

its VCE(sat) voltage, approximately 0.25 V, to 1 V before

VTTPGD is pulled HIGH. The VTTCT charging current and

CVTT set the VTTPGD delay time. The delay time can be

calculated using:

TD,VTT + (1 V * 0.25 V) @ CVTT VTTCT_Current.

The VTTCT charging current is dependent on the selection

of the oscillator frequency. See Figure 3 for a representation of

oscillator frequency and charging current versus ROSC value.

If either VTT or VTTPGD are held LOW, the internal Fault

latch will be SET, the controller will stop switching, and

VCORE will be zero.

Power Good (PWRGD)

The open−collector Power Good (PWRGD) pin is driven

by a “window−comparator” monitoring VCORE. This

comparator will transition HIGH if VCORE is within ±12%

of the nominal VID setting. After a 50

ms delay, the

comparators output will saturate the open−collector output

transistor and the PWRGD pin will be pulled LOW.

Layout Guidelines

With the fast rise, high output currents of microprocessor

applications, parasitic inductance and resistance should be

considered when laying out the power, filter and feedback

signal sections of the board. Typically, a multi−layer board

with at least one ground plane is recommended. If the layout

is such that high currents can exist in the ground plane

underneath the controller or control circuitry, the ground

plane can be slotted to route the currents away from the

controller. The slots should typically not be placed between

the controller and the output voltage or in the return path of

the gate drive. Additional power and ground planes or

islands can be added as required for a particular layout.

Gate drives experience high di/dt during switching and the

inductance of gate drive traces should be minimized. Gate

drive traces should be kept as short and wide as practical and

should have a return path directly below the gate trace.

Output filter components should be placed on wide planes

connected directly to the load to minimize resistive drops

during heavy loads and inductive drops and ringing during

transients. If required, the planes for the output voltage and

return can be interleaved to minimize inductance between

the filter and load.

The current sense signals are typically tens of milli−volts.

Noise pick−up should be avoided wherever possible.

Current feedback traces should be routed away from noisy

areas such as the switch node and gate drive signals. If the

current signals are taken from a location other than directly

at the inductor any additional resistance between the

pick−off point and the inductor appears as part of the

inherent inductor resistances and should be considered in

design calculations. The capacitors for the current feedback

networks should be placed as close to the current sense pins

as practical. After placing the CS5308 control IC, follow

these guidelines to optimize the layout and routing:

1. Place the 1

mF power−supply bypass (ceramic)

capacitors close to their associated pins: VCCL,

VCCH1, VCCH2, VCCL12.

2. Place the MOSFETs to minimize the length of the

Gate traces. Orient the MOSFETs such that the

Drain connections are away from the controller and

the Gate connections are closest to the controller.

3. Place the components associated with the internal

error amplifier (RFBK1, CFBK2, CAMP, RCMP1,

CCMP1, CCMP2, RDRP1) to minimize the trace

lengths to the pins VFB, VDRP and COMP.

4. Place the current sense components (RCS1, RCS2,

CCS1, CCS2, RCSREF, CCSREF) near the CS1, CS2,

and CSREF pins.

5. Place the frequency setting resistor (ROSC) close to

the ROSC pin. The ROSC pin is very sensitive to

noise. Route noisy traces, such as the SWNODEs and

GATE traces, away from the ROSC pin and resistor.

6. Place the VTT timing capacitor (CVTT) and

pull−up resistor (RVTT) near the VTTCT and

VTTPGD pins.

7. Place the MOSFETs and output inductors to

reduce the size of the noisy SWNODEs. There is a

trade−off between reducing the size of the

SWNODEs for noise reduction and providing

adequate heat−sinking for the synchronous

MOSFETs.

8. Place the input inductor and input capacitor(s) near

the Drain of the control (upper) MOSFETs. There

is a trade−off between reducing the size of this

node to save board area and providing adequate

heat−sinking for the control MOSFETs.

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