CS5308 datasheet(22/31 Pages) ONSEMI

22 / 31 page

CS5308

http://onsemi.com

much heatsink area as possible − all too often new designs

are found to be too hot and require re−design to add

heatsinking.

6. Adaptive Voltage Positioning

There are two resistors that determine the Adaptive

Voltage Positioning: RVFBK and RDRP. RVFBK establishes

the no−load “high” voltage position and RDRP determines

the full−load “droop” voltage.

Resistor RVFBK is connected between VCORE and the VFB

pin of the controller. At no load, this resistor will conduct the

internal bias current of the VFB pin and develop a voltage

drop from VCORE to the VFB pin. Because the error amplifier

regulates VFB to the DAC setting, the output voltage,

VCORE, will be higher by the amount IBIASVFB • RVFBK.

This condition is shown in Figure 17.

To calculate RVFBK the designer must specify the no−load

voltage increase above the VID setting (

DVNO−LOAD) and

determine the VFB bias current. Usually, the no−load voltage

increase is specified in the design guide for the processor

that is available from the manufacturer. The VFB bias current

is determined by the value of the resistor from ROSC to

ground (see Figure in the data sheet for a graph of IBIASVFB

versus R_OSC). The value of RVFBK can then be calculated:

RVFBK + DVNO−LOAD IBIASVFB

(29)

Resistor RDRP is connected between the VDRP and the

VFB pins. At no−load, the VDRP and the VFB pins will both

be at the DAC voltage so this resistor will conduct zero

current. However, at full−load, the voltage at the VDRP pin

will increase proportional to the output inductor’s current

while VFB will still be regulated to the DAC voltage. Current

will be conducted from VDRP to VFB by RDRP. This current

will be large enough to supply the VFB bias current and cause

a voltage drop from VFB to VCORE across RFBK − the

converter’s output voltage will be reduced. This condition is

shown in Figure 18.

−

RCS1

CS1

CCS1

IMAX/2

GVDRP

−

RCS2

CS2

CCS2

IMAX/2

GVDRP

CSREF

COMP

Error

Amp

VID Setting

IBIASVFB

RDRP

RVFBK

VDRP = VID +

IMAX • RL • GVDRP

VFB = VID

VCORE

IDRP

IFBK

VCORE = VID − (IDRP − IBIASVFB) w RVFBK

Figure 18. AVP Circuitry at Full−Load

IDRP = IMAX • RL • GVDRP/RDRP

IFBK = IDRP − IBIASVFB

= VID − IMAX w RL w GVDRP w RFBK/RDRP + IBIASVFB w RFBK

+ −

To determine the value of RDRP the designer must specify

the full−load voltage reduction from the VID (DAC) setting

(

DVOUT,FULL−LOAD) and predict the voltage increase at the

VDRP pin at full−load. Usually, the full−load voltage

reduction is specified in the design guide for the processor

that is available from the manufacturer. To predict the

voltage increase at the VDRP pin at full−load (DVDRP), the

designer must consider the output inductor’s resistance

(RL), the PCB trace resistance between the current sense

points (RPCB), and the controller IC’s gain from the current

sense to the VDRP pin (GVDRP):

DVDRP + IO,MAX @ (RL ) RPCB) @ GVDRP (30)

The value of RDRP can then be calculated:

RDRP +

DVDRP

(IBIASVFB ) DVOUT,FULL−LOAD RVFBK)

(31)

DVOUT,FULL−LOAD is the full−load voltage reduction

from the VID (DAC) setting.

DVOUT,FULL−LOAD is not the

voltage change from the no−load AVP setting.

7. Current Sensing

For inductive current sensing, choose the current sense

network (RCSn, CCSn, n = 1 or 2) to satisfy

RCSn @ CCSn + Lo (RL ) RPCB)

(32)

For resistive current sensing, choose the current sense

network (RCSn, CCSn, n = 1 or 2) to satisfy

RCSn @ CCSn + Lo (Rsense)

(33)

This will provide an adequate starting point for RCSn and

CCSn. After the converter is constructed, the value of RCSn

(and/or CCSn) should be fine−tuned in the lab by observing

the VDRP signal during a step change in load current. Tune

CS5308 датащи(PDF) 22 Page - ON Semiconductor

CS5308 датащи(HTML) 22 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

датащи скачать

ссылки URL