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FXPS7115D4 датащи(PDF) 20 Page - NXP Semiconductors |
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FXPS7115D4 датащи(HTML) 20 Page - NXP Semiconductors |
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20 / 72 page ![]() NXP Semiconductors FXPS7115D4 Digital absolute pressure sensor, 40 kPa to 115 kPa 7.5.3.1.1 Register read command message format MSB: bit 31; LSB: bit 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register access command Command C[3:0] Fixed bits: must = 0h Register address Register data 8-bit CRC 1 1 0 0 0 0 0 0 RA[7:1] RA[0] 0 0 0 0 0 0 0 0 CRC[7:0] Table 13. Register read command message format Bit field Definition C[3:0] Register read command = '1100' RA[7:0] RA[7:1] contains the word address of the register to be read. CRC[7:0] Read CRC Section Table 14. Register read command message bit field descriptions 7.5.3.1.2 Register read response message format MSB: bit 31; LSB: bit 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register access command Command C[0], [3:1] Basic Status Unused Data 0h Register data: contents of RA[7:1] high byte Register data: contents of RA[7:1] low byte 8-bit CRC 0 1 1 0 ST[1:0] 0 0 RD[15:8] RD[7:0] CRC[7:0] Table 15. Register read response message format Bit field Definition C[0], [3:1] Register Read Command = '0110' ST[1:0] Status RD[15:8] The contents of the register addressed by RA[7:1] high byte (RA[0] = 1) RD[7:0] The contents of the register addressed by RA[7:1] low byte (RA[0] = 0) CRC[7:0] 8-bit CRC Table 16. Register read response message bit field descriptions 7.5.3.2 Register write command The device supports a register write command. The register write command writes the value specified in RD[7:0] to the register addressed by RA[7:0]. The response to a register write command is shown in Section 7.5.3.2.2 "Register write response message format". The register write is executed and a response is transmitted on the next SPI message if and only if all of the following conditions are met: • No SPI error is detected (see Section 7.5.5.3 "SPI error") • No MISO error is detected (see Section 7.5.5.4 "SPI data output verification error") • The ENDINIT bit is cleared. – This applies to all registers except for the RESET[1:0] bits in the DEVLOCK_WR register • No invalid register request is detected as described below. FXPS7115D4 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 6.2 — 28 June 2023 20 / 72 |
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