поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

ADV7340EBZ датащи(PDF) 15 Page - Analog Devices

номер детали ADV7340EBZ
подробное описание детали  Multiformat Video Encoder, Six 12-Bit Noise Shaped Video짰 DACS
PDF  88 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADV7340EBZ датащи(HTML) 15 Page - Analog Devices

Back Button ADV7340EBZ Datasheet HTML 11Page - Analog Devices ADV7340EBZ Datasheet HTML 12Page - Analog Devices ADV7340EBZ Datasheet HTML 13Page - Analog Devices ADV7340EBZ Datasheet HTML 14Page - Analog Devices ADV7340EBZ Datasheet HTML 15Page - Analog Devices ADV7340EBZ Datasheet HTML 16Page - Analog Devices ADV7340EBZ Datasheet HTML 17Page - Analog Devices ADV7340EBZ Datasheet HTML 18Page - Analog Devices ADV7340EBZ Datasheet HTML 19Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 88 page
background image
ADV7340/ADV7341
Rev. 0 | Page 15 of 88
Y9 TO Y2/
Y9 TO Y0
Cb0
Y0
Cr0
Y1
b
a
a = 32 CLKCYCLES FOR 525p
a = 24 CLKCYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLKCYCLES FOR 525p
b(MIN) = 264 CLKCYCLES FOR 625p
P_HSYNC
P_VSYNC
P_BLANK
c
Y OUTPUT
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 15. ED-DDR, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y0
Y1
Y2
Y3
b
a
Cr2
Cb2
Cr0
Cb0
c
Y OUTPUT
P_HSYNC
P_VSYNC
P_BLANK
Y9 TO Y2/
Y9 TO Y0
C9 TO C2/
C9 TO C0
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 16. HD-SDR, 16-/20-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com