ADV7340EBZ datasheet(45/88 Pages) AD

45 / 88 page

ADV7340/ADV7341

Rev. 0 | Page 45 of 88

INPUT CONFIGURATION

The ADV7340/ADV7341 support a number of different input

modes. The desired input mode is selected using Subaddress

0x01, Bits[6:4]. The ADV7340/ADV7341 default to standard

definition only (SD only) upon power-up. Table 31 provides an

overview of all possible input configurations. Each input mode

is described in detail in the following sections.

STANDARD DEFINITION ONLY

Subaddress 0x01, Bits[6:4] = 000

Standard definition (SD) YCrCb data can be input in 4:2:2 format.

Standard definition (SD) RGB data can be input in 4:4:4 format.

A 27 MHz clock signal must be provided on the CLKIN_A pin.

Input synchronization signals are provided on the S_HSYNC

and S_VSYNC pins.

8-/10-Bit 4:2:2 YCrCb Mode

Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 0

In 8-/10-bit 4:2:2 YCrCb input mode, the interleaved pixel data

is input on Pin S9 to Pin S2/S0 (or Pin Y9 to Pin Y2/Y0, depending

on Subaddress 0x01, Bit 7), with S0/Y0 being the LSB in 10-bit

input mode. ITU-R BT.601/656 input standard is supported.

16-/20-Bit 4:2:2 YCrCb Mode

Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 1

In 16-/20-bit 4:2:2 YCrCb input mode, the Y pixel data is input

on Pin S9 to Pin S2/S0 (or Pin Y9 to Pin Y2/Y0, depending on

Subaddress 0x01, Bit 7), with S0/Y0 being the LSB in 20-bit

input mode.

The CrCb pixel data is input on Pin Y9 to Pin Y2/Y0 (or Pin C9

to Pin C2/C0, depending on Subaddress 0x01, Bit 7), with

Y0/C0 being the LSB in 20-bit input mode.

24-/30-Bit 4:4:4 RGB Mode

Subaddress 0x87, Bit 7 = 1

In 24-/30-bit 4:4:4 RGB input mode, the red pixel data is input on

Pin S9 to Pin S2/S0, the green pixel data is input on Pin Y9 to

Pin Y2/Y0, and the blue pixel data is input on Pin C9 to Pin C2/C0.

S0, Y0, and C0 are the respective bus LSBs in 30-bit input mode.

MPEG2

DECODER

CLKIN_A

S[9:0] OR Y[9:0]*

27MHz

YCrCb

ADV7340/

ADV7341

*SELECTED BY SUBADDRESS 0x01, BIT 7.

S_VSYNC,

S_HSYNC

Figure 51. SD Only Example Application

Table 31. Input Configuration

Input Mode1

000

SD Only

Y/C/S Bus Swap (0x01[7]) = 0

8-/10-Bit YCrCb2, 3

YCrCb

16-/20-Bit YCrCb2,3,4

CrCb

Y/C/S Bus Swap (0x01[7]) = 1

8-/10-Bit YCrCb2, 3

YCrCb

16-/20-Bit YCrCb2,3,4

CrCb

SD RGB Input Enable (0x87[7]) = 1

24-/30-Bit RGB4

001

ED/HD-SDR Only3,5,6,7

ED/HD RGB Input Enable (0x35[1]) = 0

16-/20-Bit YCrCb

CrCb

24-/30-Bit YCrCb

ED/HD RGB Input Enable (0x35[1]) = 1

24-/30-Bit RGB4

010

ED/HD-DDR Only

(8-/10-Bit)3, 6, 7

YCrCb

011

SD, ED/HD-SDR

(24-/30-Bit)3, 6, 7, 8

YCrCb (SD)

Y (ED/HD)

CrCb (ED/HD)

100

SD, ED/HD-DDR

(16-/20-Bit)3, 6, 7, 8

YCrCb (SD)

YCrCb (ED/HD)

111

ED Only (54 MHz)

(8-/10-Bit) 3, 6, 7

YCrCb

1 The input mode is determined by Subaddress 0x01, Bits[6:4].

2 In SD only (YCrCb) mode, the format of the input data is determined by Subaddress 0x88, Bits[4:3]. See Table 26 for more information.

3 For 8-/16-/24-bit inputs, only the eight most significant bits (MSBs) of each applicable input bus are used.

4 External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.

5 In ED/HD-SDR only (YCrCb) mode, the format of the input data is determined by Subaddress 0x33, Bit 6. See Table 19 for more information.

6 ED = enhanced definition = 525p and 625p.

7 The bus width of the ED/HD input data is determined by Subaddress 0x33, Bit 2 (0 = 8-bit, 1 = 10-bit). See Table 19 for more information.

8 The bus width of the SD input data is determined by Subaddress 0x88, Bit 4 (0 = 8-bit, 1 = 10-bit). See Table 26 for more information.

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