TMPR4955F datasheet(82/168 Pages) TOSHIBA

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Chapter 6 TX4955A System Interface

6-10

6.2.6.8

Read responses

As illustrated in Figure 6.2.11, read responses return data to processor read

requests. Read responses are external requests, strictly speaking, but there is only

one difference with other external requests: read responses do not request permission

to use the system interface. Therefore, read responses are handled separately from

other external requests and are simply referred to as read responses.

Figure 6.2.11 Read Response

6.2.7

Handling of Requests

This section will describe in detail sequences, protocol, and syntax for both processor and

external requests.

•

Load miss

•

Store miss

•

Store bit

•

Cache operation

•

Load Linked/Store Conditional

6.2.7.1

Load miss

If a processor load miss occurs in the primary cache, the processor cannot proceed to

the next process if the cache line that contains the loaded data elements is not received

from the external agent.

If the current cache line set in which the write back bit (W bit) is set is replaced by a

new cache line, the current cache line must be written back.

The processor checks the coherency properties in the TLB entries for pages

including the requested cache lines. If the coherency properties are non-coherent, then

a non-coherent read request is issued. Table 6.2.1 indicates the measures that can be

taken when a load miss occurs in the primary cache.

Table 6.2.1 Load Miss to the Primary Cache

State of the replaced data cache line

Page Properties

Dirty (W = 0)/Invalid

Dirty (W = 1)

Non-coherent

NCR

NCR/W

NCR: Processor non-coherent, block read request

NCR/W: Processor non-coherent, block write requests continue after the block read

request

6.2.7.2

Store miss

When a store miss occurs in the primary cache, the processor cannot proceed to the

next process if it does not receive from the external agent a cache line that includes a

store target address. The processor checks the coherency properties in the TLB entries

for pages including the requested cache line, then confirms whether to invalidate write

transactions to that cache line or not.

After that, the processor executes one of the following requests:

1. Read request

TX4955A

External agent

2. Read response

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