TMPR4955F datasheet(52/168 Pages) TOSHIBA

52 / 168 page

Chapter 3 Initialization Interface

3-2

3.2

Reset Signal Description

This section describes the two reset signals, ColdReset

ColdReset

ColdReset* and Reset

Reset

Reset*.

•

ColdReset

ColdReset*: the ColdReset

ColdReset

ColdReset* signal must be asserted(Note) (low) to reset the processor.

Internal clock begins to cycle and is synchronized with the deasserted edge

(high) of ColdReset

ColdReset

ColdReset*. ColdReset

ColdReset

ColdReset* can be asserted and deasserted

asynchronously with the rising edge of MasterClock

MasterClock

MasterClock.

•

Reset

Reset*: the Reset

Reset

Reset* signal is asserted synchronously to initiate a warm reset. The

Reset

Reset* signal must be deasserted synchronously with MasterClock

MasterClock

MasterClock.

Note: Asserted means the signal is true, or in its valid state. For example, the low-active Reset*

signal is said to be asserted when it is in a low (true) state.

3.2.1

Cold Reset

A cold reset is used to completely reset the processor, including processor clocks.

Information about saving processor states is given below.

Once power to the processor is established, the ColdReset

ColdReset

ColdReset* signal is asserted for 64,000

MasterClock

MasterClock cycles to ensure time for the processor clocks to lock to the input MasterClock

MasterClock

MasterClock.

ColdReset

ColdReset* can be asserted and deasserted asynchronously with the rising edge of

MasterClock

MasterClock.

Reset

Reset* can be asserted/deasserted when ColdReset

ColdReset

ColdReset* is asserted, but its value must not be

changed during the reset sequence.

Upon reset, the processor becomes bus master and drives the SysAD

SysAD

SysAD bus. After Reset

Reset

Reset* is

deasserted, the processor branches to the Reset exception vector and begins executing the

Reset exception code.

For information on the bit states during a cold reset, see the section on Cold Reset

exceptions in CPU Exception Processing.

3.2.2

Warm Reset

A warm reset is used to reset the processor without affecting the clocks; in other words, a

warm reset is a logic reset.

Asserting the Reset

Reset

Reset* signal resets the processor without disrupting the clocks and allows

the processor to retain as much of its state as possible for debugging. (For information on

saving the processor states, see the section on Soft Reset exception in CPU Exception

Processing.) Because asserting the Reset

Reset

Reset* signal results in an immediate warm reset,

multicycle instructions such as cache misses or floating-point instructions may be aborted

and some data lost as a result.

A warm reset is started by assertion of the Reset

Reset

Reset* pin. Reset

Reset

Reset* must be asserted for a

minimum of 16 cycles, and must be asserted and deasserted synchronously with

MasterClock

MasterClock. In general, data in the processor is preserved for debugging purposes.

Upon reset, the processor becomes bus master and drives the SysAD

SysAD

SysAD bus. After Reset

Reset

Reset* is

deasserted, the processor branches to the Reset exception vector and begins executing the

reset exception code.

If Reset

Reset

Reset* is asserted in the middle of a SysAD

SysAD

SysAD transaction, care must be taken to reset all

external agents to avoid SysAD

SysAD

SysAD bus contention.

Figure 3.2.1 and Figure 3.2.2 show the timing diagrams for the cold and warm resets.

TMPR4955F датащи(PDF) 52 Page - Toshiba Semiconductor

TMPR4955F датащи(HTML) 52 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL