TMPR4955F datasheet(75/168 Pages) TOSHIBA

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Chapter 6 TX4955A System Interface

6-3

6.2.3

Issue cycle

Two types of processor issue cycles exist with the TX4955A.

•

Processor read request issue cycles.

•

Processor write request issue cycles.

The TX4955A judges the issue cycle of the processor read request by sampling the

RdRdy* signal. It also judges the issue cycle of the processor write request by sampling the

WrRdy* signal from the external agent.

As illustrated in Figure 6.2.2, RdRdy* must be asserted two cycles before the processor

read request address cycle in order to define the address cycle as an issue cycle.

Figure 6.2.2 RdRdy* Signal Status in case of Read Request

As illustrated in Figure 6.2.3, WrRdy* is asserted two cycles before the initial address

cycle of the processor write request, and the address cycle must be defined as the issue

cycle.

Figure 6.2.3 WrRdy* Signal Status in case of Write Request

The TX4955A repeats the request address cycle until the conditions of the valid issue

cycle are met. If the processor request is a data transmission, then data transmission starts

at the point when the issue cycle is complete. There is only one issue cycle no matter what

the processor request is.

The TX4955A accepts external requests even while trying to issue processor requests. If

the external agent asserts ExtRqst*, the processor responds to the external agent by

releasing the system interface and going into the slave state. Rules relating to the issue

cycle of processor requests are strictly applied in determining the processor run operation

as well. The TX4955A performs one of the following:

Address

Issue

Cycle

234

Cycle

Master Clock

SysAD Bus

RdRdy*

ValidOut*

Address

Issue

Cycle

234

Cycle

Master Clock

SysAD Bus

WrRdy*

ValidOut*

Data

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