TMPR4955F datasheet(80/168 Pages) TOSHIBA

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Chapter 6 TX4955A System Interface

6-8

The external agent must be able to accept processor read requests at any time if

either of the two following conditions is met.

•

There is no processor read request that is on hold.

•

The RdRdy* signal is asserted for 1 cycle 2 cycles before the issue cycle.

6.2.6.4

Processor write request

When the processor issues a write request, the specified resources are accessed,

then the data are written to those resources.

Processor write requests are complete when the final data word is transferred to the

external agent.

The external agent must be able to accept processor write requests at any time if

either of the two following conditions are met.

•

There is no processor read request that is on hold.

•

The WrRdy* signal is asserted for 1 cycle 2 cycles before the issue cycle.

6.2.6.5

External requests

As illustrated in Figure 6.2.9, there are three types of external request: read, write,

and null. This section will explain read responses, which are special external request

cases.

Figure 6.2.9 External Requests

Read requests are used to call 1-word data from processor internal resources. Write

requests are used to write 1-word data to the processor internal resources. Null

requests are requests that do not require processor operation.

As illustrated in Figure 6.2.10, the processor uses arbitration signals ExtRqst* and

Release* to control the flow of external requests. The external agent cannot issue

external requests unless access privileges to the system interface are obtained. In

order to do so, the external agent asserts the ExtRqst* signal, then waits until the

processor asserts the Release* signal for 1 cycle.

Figure 6.2.10 External Requests

External request

・ Read

・ Write

・ Null

TX4955A

External agent

1. External system requests

bus access privileges by

asserting the ExtRqst*

signal

TX4955A

External agent

2. Processor grants access

privileges by asserting

the Release* signal

3. External system issues

external request

4. Processor obtains bus

access privileges again

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