ICS557-08

2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1

PCIE MULTIPLEXER

IDT® 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1

3

ICS557-08

REV L 112111

Application Information

Decoupling Capacitors

As with any high-performance mixed-signal IC, the

ICS557-08 must be isolated from system power supply

noise to perform optimally.

Decoupling capacitors of 0.01µF must be connected

between each VDD and the PCB ground plane.

PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

Each 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible. No vias should be used between decoupling

capacitor and VDD pin. The PCB trace to VDD pin should

be kept as short as possible, as should the PCB trace to the

ground via. Distance of the ferrite bead and bulk decoupling

from the device is less critical.

2) An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers (the ferrite bead and bulk decoupling capacitor can be

mounted on the back). Other signal traces should be routed

away from the ICS557-08.

This includes signal traces just underneath the device, or on

layers adjacent to the ground plane layer used by the device.

External Components

A minimum number of external components are required for

proper operation. Decoupling capacitors of 0.01

μF should

be connected between VDD and GND pins as close to the

device as possible.

Current Reference Source Rr (Iref)

If board target trace impedance (Z) is 50

Ω, then Rr = 475Ω

(1%), providing IREF of 2.32 mA, output current (IOH) is

equal to 6*IREF.

Load Resistors RL

Since the clock outputs are open source outputs, 50

Ω

external resistors to ground are to be connected at each

clock output.

Output Termination

The PCI-Express differential clock outputs of the ICS557-08

are open source drivers and require an external series

resistor and a resistor to ground. These resistor values and

their allowable locations are shown in detail in the

PCI-Express Layout Guidelines section.

The ICS557-08 can also be configured for LVDS compatible

voltage levels. See the LVDS Compatible Layout

Guidelines section.