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AIN−

0

4095

2V

MODE 2, CON[1:0] = 10

AIN−

0

4095

1V

MODE 1, CON[1:0] = 01

AIN+

AIN+

Signal Processing Chain (Sample and Hold, ADC)

THS1230

SLAS291B – OCTOBER 2000 – REVISED MARCH 2004

Table 1. Input Modes of Operation

MODE

CON1

CON0

MODE OF OPERATION

0

0

0

Device powered down

1

0

1

Differential mode

× 1

2

1

0

Differential mode

× 0.5

3

1

1

Not used

Modes 1 and 2 are shown in Figure 14.

Figure 14. Input Mode Configurations

The gain of the sample and hold changes with the CON1 and the CON0 inputs. Table 2 shows the gain of the

sample and hold and the levels applied at the AIN+ and AIN– analog inputs for Mode 1 and Mode 2. The

common mode level for the two analog inputs is at AVDD/2.

Table 2. Input Mode Switching

(AIN+) – (AIN–)

(AIN+) – (AIN–)

MODE

CON1

CON0

S/H GAIN

MIN

MAX

1

0

1

–1 V

1 V

×1

2

1

0

–2 V

2 V

×0.5

The user-chosen operating configuration and reference voltages determine what input signal voltage range the

THS1230 can handle.

The following sections explain both the internal signal flow of the device and how the input signal span is related

to the ADC reference voltages, as well as the ways in which the ADC reference voltages can be buffered

internally or externally applied.

Figure 15 shows the signal flow through the sample and hold unit and the PGA to the ADC core.

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