IDTTM/ICSTM Programmable FTG for Differential P4

TM CPU, PCI-Express & SATA Clocks

ICS9FG107

REV F 08/21/07

ICS9FG107

Programmable FTG for Differential P4

TM CPU, PCI-Express & SATA Clocks

9

Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus

DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =

HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is

programmed to a '1', DIFoutputs will be tri-stated.

DIF_STOP# - Assertion (transition from '1' to '0')

With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the

de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of

interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a

voltage greater than 200mV.

DIF_STOP# - De-assertion (transition from '0' to '1')

DIF_STOP#

DIF

DIF#

DIF_Stop#

Tdrive_DIF_Stop, 10nS >200mV

DIF

DIF#

DIF Internal