поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

ICS9FG107 датащи(PDF) 6 Page - Renesas Technology Corp

номер детали ICS9FG107
подробное описание детали  Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
PDF  19 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS9FG107 датащи(HTML) 6 Page - Renesas Technology Corp

Back Button ICS9FG107 Datasheet HTML 2Page - Renesas Technology Corp ICS9FG107 Datasheet HTML 3Page - Renesas Technology Corp ICS9FG107 Datasheet HTML 4Page - Renesas Technology Corp ICS9FG107 Datasheet HTML 5Page - Renesas Technology Corp ICS9FG107 Datasheet HTML 6Page - Renesas Technology Corp ICS9FG107 Datasheet HTML 7Page - Renesas Technology Corp ICS9FG107 Datasheet HTML 8Page - Renesas Technology Corp ICS9FG107 Datasheet HTML 9Page - Renesas Technology Corp ICS9FG107 Datasheet HTML 10Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 19 page
background image
IDTTM/ICSTM Programmable FTG for Differential P4
TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
ICS9FG107
Programmable FTG for Differential P4
TM CPU, PCI-Express & SATA Clocks
6
I
2C Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RW
Pin 27
Bit 6
RW
Pin 5
Bit 5
RW
Pin 44
Bit 4
RW
Pin 7
Bit 3
RW
Off
On
Pin 26
Bit 2
RW
Hardware
Select
Software
Select
0
Bit 1
RW
Driven
Hi-Z
0
Bit 0
RW
Down
Center
Pin 45
Notes:
1. These bits reflect the latched state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
I
2C Table: Output Enable Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
PCICLK0
Output Enable
RW
Stop Low
Enable
1
Bit 6
DIF_6
Output Enable
RW
Disable
Enable
1
Bit 5
DIF_5
Output Enable
RW
Disable
Enable
1
Bit 4
DIF_4
Output Enable
RW
Disable
Enable
1
Bit 3
DIF_3
Output Enable
RW
Disable
Enable
1
Bit 2
DIF_2
Output Enable
RW
Disable
Enable
1
Bit 1
DIF_1
Output Enable
RW
Disable
Enable
1
Bit 0
DIF_0
Output Enable
RW
Disable
Enable
1
I
2C Table: Output Stop Mode Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
PCICLK1
Output Enable
RW
Stop Low
Enable
1
Bit 6
DIF_6
Stop Mode
RW
Free-run
Stop-able
0
Bit 5
DIF_5
Stop Mode
RW
Free-run
Stop-able
0
Bit 4
DIF_4
Stop Mode
RW
Free-run
Stop-able
0
Bit 3
DIF_3
Stop Mode
RW
Free-run
Stop-able
0
Bit 2
DIF_2
Stop Mode
RW
Free-run
Stop-able
0
Bit 1
DIF_1
Stop Mode
RW
Free-run
Stop-able
0
Bit 0
DIF_0
Stop Mode
RW
Free-run
Stop-able
0
44
7
Byte 0
27
5
26
Spread Enable
1
-
Enable Software Control of Frequency,
Spread Enable and Spread Type
DIF_STOP# drive mode
45
DWNSPRD#
1
Byte 1
8
12,13
17,18
20,21
30,29
33,32
39,38
42,41
Byte 2
9
12,13
17,18
20,21
30,29
33,32
See Frequency
Selection Table, Page 1
FS3
1
FS2
1
FS1
1
FS0
1
39,38
42,41



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com