IDTTM/ICSTM Programmable FTG for Differential P4

TM CPU, PCI-Express & SATA Clocks

ICS9FG107

REV F 08/21/07

ICS9FG107

Programmable FTG for Differential P4

TM CPU, PCI-Express & SATA Clocks

7

I

2C Table: Frequency Select Readback Register

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

SEL14M_25M#

1

(FS3)

State of pin 27

R

Pin 27

Bit 6

FS2

1

State of pin 6

R

Pin 5

Bit 5

FS1

1

State of pin 44

R

Pin 44

Bit 4

FS0

1

State of pin 7

R

Pin 7

Bit 3

SPREAD

1

State of pin 26

R

Off

On

Pin 26

Bit 2

RX

Bit 1

RX

Bit 0

DWNSPRD

1

State of pin 45

R

Down

Center

Pin 45

Notes:

1. These read-only bits always reflect the latched state of the corresponding pins at power up.

I

2C Table: Vendor & Revision ID Register

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

RID3

R

-

-

0

Bit 6

RID2

R

-

-

0

Bit 5

RID1

R

-

-

0

Bit 4

RID0

R

-

-

0

Bit 3

VID3

R

-

-

0

Bit 2

VID2

R

-

-

0

Bit 1

VID1

R

-

-

0

Bit 0

VID0

R

-

-

1

I

2C Table: DEVICE ID

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

R0

Bit 6

R0

Bit 5

R0

Bit 4

R0

Bit 3

R0

Bit 2

R1

Bit 1

R1

Bit 0

R1

RESERVED

RESERVED

Device ID = 07 Hex

Bit 7 is MSB

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

5

27

7

44

Byte 3

26

RESERVED

RESERVED

RESERVED

RESERVED

45

Byte 4

-

REVISION ID

-

-

-

-

VENDOR ID

-

-

-

Byte 5

-

-

-

-

-

-

-

See Frequency

Selection Table, Page 1

-