PCAL9714 datasheet(13/56 Pages) NXP

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NXP Semiconductors

PCAL9714

Ultra low-voltage translating 14-bit SPI I/O expander with Agile I/O features, interrupt output, and

reset

Bit

Default

Table 17. Current control port 1A register (address 42h)...continued

Bit

Symbol

CC1.5

CC1.4

Default

Table 18. Current control port 1B register (address 43h)

6.4.6 Input latch registers (44h, 45h)

The input latch registers (registers 44 and 45) enable and disable the input latch of the I/O pins. These

registers are effective only when the pin is configured as an input port. When an input latch register bit is 0,

the corresponding input pin state is not latched. A state change in the corresponding input pin generates an

interrupt. A read of the input register clears the interrupt. If the input goes back to its initial logic state before the

input port register is read, then the interrupt is cleared.

When an input latch register bit is 1, the corresponding input pin state is latched. A change of state of the input

generates an interrupt and the input logic value is loaded into the corresponding bit of the input port register

(registers 0 and 1). A read of the input port register clears the interrupt. If the input pin returns to its initial logic

state before the input port register is read, then the interrupt is not cleared and the corresponding bit of the input

port register keeps the logic value that initiated the interrupt. See Figure 12

For example, if the P0_4 input was as logic 0 and the input goes to logic 1 then back to logic 0, the input port

0 register will capture this change and an interrupt is generated (if unmasked). When the read is performed on

the input port 0 register, the interrupt is cleared, assuming there were no additional input(s) that have changed,

and bit 4 of the input port 0 register will read ‘1’. The next read of the input port register bit 4 register should now

read ‘0’.

An interrupt remains active when a non-latched input simultaneously switches state with a latched input and

then returns to its original state. A read of the input register reflects only the change of state of the latched input

and also clears the interrupt. The interrupt is not cleared if the input latch register changes from latched to non-

latched configuration.

If the input pin is changed from latched to non-latched input, a read from the input port register reflects the

current port logic level. If the input pin is changed from non-latched to latched input, the read from the input

read operation is described in Section 6.10.1.2.

Bit

Symbol

L0.7

L0.6

L0.5

L0.4

L0.3

L0.2

L0.1

L0.0

Default

Table 19. Input latch port 0 register (address 44h)

Bit

Symbol

L1.5

L1.4

L1.3

L1.2

L1.1

L1.0

Default

Table 20. Input latch port 1 register (address 45h)

PCAL9714

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 1 May 2023

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