NXP Semiconductors

PCAL9714

Ultra low-voltage translating 14-bit SPI I/O expander with Agile I/O features, interrupt output, and

reset

[1]

For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V or 3.6 V VDD) and Tamb = 25 °C. Except for IDD, the typical values are at VDD(P)

= VDD(SPI) = 3.3 V and Tamb = 25 °C.

[2]

The total current sourced by all I/Os must be limited to 160 mA.

[3]

Each I/O must be externally limited to a maximum of 25 mA and each octal (P0_0 to P0_7 and P1_0 to P1_5) must be limited to a maximum current of

100 mA, for a device total of 200 mA.

[4]

Typical value for Tamb = 25 °C. VOL = 0.4 V and VDD(SPI) = VDD(P) = 3.3 V. Typical value for VDD(SPI) = VDD(P) < 2.5 V, VOL = 0.6 V.

[5]

Internal pullup/pulldown resistors disabled.

[6]

Value not tested in production, but guaranteed by design and characterization.

Tamb = -40 °C to +125 °C; VDD(SPI) = 0.8 V to 3.6 V; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ [1]

Max

Unit

VIK

input clamping voltage

II = -18 mA

-1.2

-

-

V

VPOR

power-on reset voltage

VI = VDD(P) or VSS; IO = 0 mA

-

1.2

1.5

V

P port; IOH = -8 mA; CCX.X = 11b

VDD(P) = 1.65 V

1.2

-

-

V

VDD(P) = 2.3 V

1.8

-

-

V

VDD(P) = 3 V

2.6

-

-

V

VDD(P) = 4.5 V

4.1

-

-

V

P port; IOH = -2.5 mA and CCX.X = 00b;

IOH = -5 mA and CCX.X = 01b;

IOH = -7.5 mA and CCX.X = 10b;

IOH = -10 mA and CCX.X = 11b;

VDD(P) = 1.65 V

1.1

-

-

V

VDD(P) = 2.3 V

1.7

-

-

V

VDD(P) = 3 V

2.5

-

-

V

VDD(P) = 4.5 V

4.0

-

-

V

SDOUT port

VDD(SPI) ≤ 1.65 V, IOH = -0.4 mA

0.8 x

VDD(SPI)

-

-

V

VOH

HIGH-level output voltage

[2]

VDD(SPI) > 1.65 V, IOH = -4 mA

VDD(SPI) -

0.3

-

-

V

P port; IOL = 8 mA; CCX.X = 11b

VDD(P) = 1.65 V

-

-

0.45

V

VDD(P) = 2.3 V

-

-

0.25

V

VDD(P) = 3 V

-

-

0.25

V

VDD(P) = 4.5 V

-

-

0.20

V

P port; IOL = 2.5 mA and CCX.X = 00b;

IOL = 5 mA and CCX.X = 01b;

IOL = 7.5 mA and CCX.X = 10b;

IOL = 10 mA and CCX.X = 11b;

VDD(P) = 1.65 V

-

-

0.5

V

VDD(P) = 2.3 V

-

-

0.3

V

VDD(P) = 3 V

-

-

0.25

V

VDD(P) = 4.5 V

-

-

0.2

V

VOL

LOW-level output voltage

[2]

SDOUT port

Table 49. Static characteristics for PCAL9714HN/Q900

PCAL9714

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Product data sheet

Rev. 1.0 — 1 May 2023

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