PCAL9714 datasheet(16/56 Pages) NXP

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NXP Semiconductors

PCAL9714

Ultra low-voltage translating 14-bit SPI I/O expander with Agile I/O features, interrupt output, and

reset

Bit

Symbol

reserved

ODEN1

ODEN0

Default

Table 29. Output port configuration register (address 4Fh)

6.4.12 Interrupt edge registers (50h, 51h, 52h, 53h)

These registers determine what action on an input pin will cause an interrupt along with the Interrupt Mask

registers (4Ah and 4Bh). If the Interrupt Mask is enabled (a 0 in the Mask register) and the action at the

corresponding pin matches the required activity, the INT output will become active. The default value for each

pin is 0 or level triggered, meaning a level change on the pin will cause an interrupt event. A level triggered

action means a change in logic state (HIGH-to-LOW or LOW-to-HIGH), since the last read of the Input port

(00h or 01h). If the Interrupt edge register entry is set to 03h, any edge, positive- or negative-going, causes

an interrupt event. If an entry is 01h, only a positive-going edge will cause an interrupt event, while a 02h will

require a negative-going edge to cause an interrupt event. A register write operation is described in 6.10.1.1. A

Bit

Symbol

IE0.3

IE0.2

IE0.1

IE0.0

Default

Table 30. Interrupt edge port 0A register (address 50h)

Bit

Symbol

IE0.7

IE0.6

IE0.5

IE0.4

Default

Table 31. Interrupt edge port 0B register (address 51h)

Bit

Symbol

IE1.3

IE1.2

IE1.1

IE1.0

Default

Table 32. Interrupt edge port 1A register (address 52h)

Bit

Symbol

IE1.5

IE1.4

Default

Table 33. Interrupt edge port 1B register (address 53h)

6.4.13 Interrupt clear registers (54h, 55h)

These write-only registers clear individual interrupt sources. Setting an individual bit or any combination of bits

to logic 1 will reset the corresponding interrupt source, so if that source was the only event causing an interrupt,

the INTwill be cleared. After writing a logic 1 the bit returns to logic 0. A register write operation is described in

Section 6.10.1.1. A register read operation is described in Section 6.10.1.2.

PCAL9714

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 1 May 2023

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