CS5920 datasheet(137/160 Pages) AMCC

137 / 160 page

S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

137

Data Book

Figure 76. Active Mode 32-Bit PCI Write w/PTWAIT#

Clock by Clock description of Figure 16

Clock 1:

The S5920 drives PTATN# and PTBURST#

active (low), indicating the start of a PCI to Add-On

data transfer with more than one data cycle. PTBE[3:0]

and PTNUM[1:0] are driven to their appropriate values

for this transfer. PTWR is driven high indicating a

Pass-Thru write.

Clock 2:

Since this region does not have PTADR#

enabled as an output and PTWAIT# is high at the ris-

ing edge of clock 2, the first data transfer is indicated

by driving DXFR# low and the data on the data bus

DQ[31:0] .

Clock 3:

DXFR# is sampled active by the Add-On

device which indicates that the Add-On device must

latch the first data word at the rising edge of this clock.

Valid data is determined by decoding the PTBE[3:0]#

lines. The Add-On device drives PTWAIT# active (low)

requesting a wait state on the next cycle.

Clock 4:

DXFR# is sampled active (low) by the Add-

On device which indicates that the Add-On device

must latch the second data word at this clock edge.

The S5920 tri-states its output bus since PTWAIT#

was inactive (high) at the rising edge of clock 4. Addi-

tionally, the S5920 deasserts DXFR# indicating that no

data transfer will occur on the next clock edge (this is

because this cycle is a wait state since PTWAIT# was

active (low) at the rising edge of clock 4. The Add-On

device deasserts PTWAIT# indicating no wait state on

the next clock.

Clock 5:

No data transfer takes place at the rising

edge of clock 5 since the previous cycle was an Add-

On initiated wait state (because PTWAIT# was active

(low) at the rising edge of clock 4). The S5920 asserts

DXFR# and drives the third data onto the DQ bus

since PTWAIT# was inactive (high) at the rising edge

of clock 5. The Add-On device drives PTWAIT# active

(low) requesting a wait state on the next cycle.

Clock 6:

DXFR# is sampled active by the Add-On

device which indicates that the Add-On device must

latch the third data word at the rising edge of this

clock. The S5920 drives DXFR# inactive and tri-states

the DQ bus since PTWAIT# was active (low) at the ris-

ing edge of clock 6. The Add-On keeps PTWAIT#

asserted indicating it wants to add a wait state on the

next cycle.

Clock 7:

No data transfer takes place on the rising

edge of this clock since the previous cycle was an

Add-On initiated wait state (because PTWAIT# was

active (low) at the rising edge of clock 6).

Clock 8:

No data transfer takes place on the rising

edge of this clock since the previous cycle was an

Add-On-initiated wait state (because PTWAIT# was

active (low) at the rising edge of clock 7). DXFR# is

driven active (low) and the fourth data is driven onto

the DQ bus since PTWAIT# was inactive (high) at the

rising edge of clock 8. PTBURST# is driven inactive

(high) indicating that after this data word is transferred,

there is only one data word left to transfer.

ADCLK

PTATN#

PTBURST#

PTNUM[1:0]

PTWR

PTBE[3:0]#

DXFR#

DQ[31:0]

PTADR#

PTWAIT#

Data3

01b

DATA4

DATA1

Data1

Data2

Data4

Data5

DATA2

DATA3

DATA5

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