CS5920 datasheet(132/160 Pages) AMCC

132 / 160 page

S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

132

Data Book

Clock 5:

The Add-On logic latches BYTE1. RD# and

BE2# are sampled asserted by the S5920, so BYTE2

of the APTD is driven on DQ[7:0] and PTBE2# is deas-

serted. The Add-On device asserts RD# and BE3#,

thus requesting that BYTE3 of the APTD be driven on

the DQ bus during the next cycle. PTRDY# is also

asserted, indicating that the transfer is complete.

Clock 6:

The Add-On logic latches BYTE2. RD# and

BE3# are sampled asserted by the S5920, so BYTE3

of the APTD is driven on DQ[7:0]. PTRDY# is sampled

asserted, so the previous transfer is complete. The

PTBE# signals are updated to indicate which bytes are

valid for the next transfer (in this case, all bytes are

valid for the second DWORD, so PTBE# = 0h). The

S5920 deasserts PTBURST#, as it only has one

DWORD left to transfer. The Add-On device asserts

RD# and BE3#, thus requesting that BYTE3 of the

second DWORD in the APTD be driven on the DQ bus

during the next cycle.

Clock 7:

The Add-On logic latches BYTE3 of the first

DWORD. RD# and BE3# are sampled asserted by the

S5920, so BYTE3 of the second DWORD in the APTD

is driven on DQ[7:0] and PTBE3# is deasserted. The

Add-On device asserts RD# and BE2#, thus request-

ing that BYTE2 of the APTD be driven on the DQ bus

during the next cycle.

Clock 8:

The Add-On logic latches BYTE3 of the sec-

ond DWORD. RD# and BE2# are sampled asserted

by the S5920, so BYTE2 of the APTD is driven on

DQ[7:0] and PTBE2# is deasserted. The Add-On

asserts RD# and BE1#, thus requesting that BYTE1 of

the APTD be driven on the DQ bus during the next

cycle.

Clock 9:

The Add-On logic latches BYTE2 of the sec-

ond DWORD. RD# and BE1# are sampled by the

S5920, so BYTE1 of the APTD is driven on DQ[7:0]

and PTBE1# is deasserted. The Add-On asserts RD#

and BE0#, thus requesting that BYTE0 of the APTD be

driven on the DQ bus during the next cycle. PTRDY#

is also asserted, indicating that the transfer is com-

plete. As PTBURST# is already deasserted, the Add-

On recognizes that this is the last transfer.

Clock 10:

The Add-On logic latches BYTE1 of the

second DWORD. RD# and BE0# are sampled by the

S5920, so BYTE0 of the APTD is driven on DQ[7:0].

PTRDY# is sampled asserted, so the previous transfer

is complete. The PTBE# signals are updated to indi-

cate which bytes are valid for the next transfer (in this

case, there is no more valid data to transfer, so PTBE

= Fh). The S5920 deasserts PTATN#, as it has no data

left to transfer. The Add-On device deasserts RD#,

BE#, ADR[6:2], SELECT# as the data transfer is

complete.

Clock 11:

The Add-On logic latches BYTE0 of the

second DWORD. PTATN# and PTBURST# both deas-

serted indicate tha t the Pass-T hru transfer is

complete. The PCI can start another access on the

next clock cycle. For 16-bit peripheral devices, the

byte steering works in the same way. Because the

Add-On data bus is 16 bits wide, only two 16-bit cycles

are required to access the entire APTD Register. Two

byte enables can be asserted during each access.

Figure 12 shows a Pass-Thru read operation for a

region defined for a 16-bit Add-On bus interface. As

the 16-bit device is connected only to DQ[15:0], the

device must access the APTD one word at a time. The

Add-On must be capable of latching the upper 16 bits

of the APTA (if they are needed).

The PCI initiator has requested a 32-bit burst read

from Pass-Thru region three. All PTBE#s are asserted.

Clock 1:

The Add-On begins by reading the APTA

are driven on the DQ bus.

Clock 2:

Turn-around cycle, preventing potential bus

contention on the DQ bus.

Clock 3:

The Add-On initiates the write by asserting

WR#, SELECT#, BE[3:0]# = “1100”, ADR[6:2] = 2Ch

and the low word of the first DWORD to be transferred

(D0-LO).

Clock 4:

The S5920 updates the PTBE#s to indicate

that the low word was provided, and that the upper

word is still required. The Add-On drives the upper

word (D0-HI), and activates the appropriate byte

enables, BE# = 0011 The Add-On also asserts

PTRDY#, indicating that it is done with the current

DWORD, and to advance the FIFO pointer and pre-

pare for the second DWORD.

Clock 5:

The PTBE#s are updated to indicate that the

next DWORD to be transferred requires all bytes. The

Add-On drives DQ[15:0] with the lower word of the

second DWORD (D1-LO), and the byte-enables indi-

cate t he s ame, B E# = 1100. The A dd-On als o

deasserts PTRDY#. This process continues until the

transfer is complete and all words have been written.

Endian Conversion

Endian conversion can be enabled/disabled for each

Pass-Thru Region. It is controlled by bits 6, 14, 22 and

30 of the PTCR. The default endian type for the S5920

is Little Endian. For this reason, the default values in

the PTCR are for Little Endian. If Big Endian is

selected, the Pass-Thru data and byte-enable inter-

face will be converted to Big Endian type.

CS5920 датащи(PDF) 132 Page - Applied Micro Circuits Corporation

CS5920 датащи(HTML) 132 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL