ADIS16201SLASHPCB datasheet(24/32 Pages) AD

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ADIS16201

Data Sheet

Rev. C | Page 24 of 32

SMPL_PRD Register Definition

Address

Default1

Format

Access

0x37, 0x36

0x000A

N/A

R/W

1 Default is valid only until the first register write cycle.

After using the manual flash update (COMMAND[3]), the data

within this register is nonvolatile, allowing for data recovery

upon reset. The initial value is set to 0x0A upon initial power-

up, allowing for a sample period of ~744 μs.

Table 24. SMPL_PRD Bit Descriptions

Bit

Description

15:8

Not used.

ADC time base control.

0: tB = 122.1 μs

1: tB = 3.784 ms .

6:0

ADC sample period control (NS).

Relationship to the sample period control:

tS = tB × (NS + 1)

FILTERING CONTROL

The ADIS16201 has the ability to perform basic filtering on the

seven output data variables through the AVG_CNT control

average filter. The size of the data being averaged (number of

filter taps) is determined through the AVG_CNT control

and, thus, one output variable cannot be filtered differently

from another.

The number of taps (N) within the moving average filter is

calculated as

CNT

AVG



where AVG_CNT is shown as a decimal value. With AVG_CNT

set to 00h, N is reduced to 1, which effectively disables the

moving average filter.

At the other extreme, when AVG_CNT is set to its maximum

setting of 08h, N increases to 256, effectively reducing the

apparent bandwidth by 256. Note that the contribution from

each tap is set to 1/(N) allowing for unity gain in the filter

response. The frequency response of the moving average filter is

given as:

)

sin(

)

sin(

)

(







The more taps, the more poles, thus the steeper the slope of the

roll-off. Use caution with this filter mechanism because the

amplitudes of the sideband peaks within the stop band are not

reduced with an increasing number of taps, potentially allowing

for high frequency components to leak through. Sample

frequency response plots for the moving average filter, utilizing

various numbers of taps, are detailed in Figure 37.

1.0

H(f)

–0.5

00.5

f/fs

FREQUENCY (Hz)

0.5

0.1

0.2

0.3

0.4

N = 2

N = 4

N = 16

Figure 37. Number of Taps vs. Sample Frequency Response

AVG_CNT Register Definition

Address

Default1

Format

Access

0x39, 0x38

0x0006

Binary

R/W

1 Default is valid only until the first register write cycle.

The AVG_CNT register contains information that represents

the number of averages to be applied to the output data. The

number of averages can be calculated by powers of 2. For

example, the default value of the register, 4, would result in 16

averages applied to the output data. The number of averages can

be set to 1, 2, 4, 8, 16, 32, 64, 128, and 256.

Table 25. AVG_CNT Bit Description

Bit

Description

15:4

Not used

3:0

Data bits (maximum = 1000, or a decimal value of 8)

POWER-DOWN CONTROL

The ADIS16201 has the ability to power down for user-defined

amounts of time, using the PWR_MDE control register. The

amount of time specified by the PWR_MDE control register is

equal to the binary count of the 8-bit control word multiplied

by 0.5 seconds. Therefore, the 255 codes cover an overall

shutdown time period of 127.5 seconds. The PWR_MDE

subsequent wake-ups from the power-down period. By setting

the PWR_MDE control register to a non-zero state, the

ADIS16201 automatically powers down once the next sample

period is completed and the seven data output registers are

updated.

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