ADIS16201SLASHPCB datasheet(15/32 Pages) AD

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Data Sheet

ADIS16201

Rev. C | Page 15 of 32

BASIC OPERATION

The ADIS16201 is designed for simple integration into indus-

trial system designs, requiring only a 3.3 V power supply and a

4-wire, industry standard, serial peripheral interface (SPI).

Registers that are accessed using the SPI interface facilitate all of

the input/output functions on the ADIS16201. Each of these

registers is assigned a unique address and data format tailored

for its specific function. The SPI port operates in a full duplex

mode; data is clocked out of the DOUT pin at the same time

command/address data is clocked in through the DIN pin. For

more information on basic SPI port operation, see the

Applications section.

DATA OUTPUT REGISTER ACCESS

For the most basic operation of the ADIS16201, output data

registers require only read commands for accessing calibrated

sensor data, along with the temperature, power supply, and

auxiliary analog input channel data. Each read command

requires two full 16-bit cycles. The first cycle is for transmitting

the register address, and the second cycle is for reading the data.

Table 6 displays the appropriate bit map for the read command.

Bit A0 through Bit A5 contain the address of the register being

accessed. The appropriate sequencing for each SPI signal (CS,

SLCK, DIN, and DOUT) during a read command can be found

in Figure 34.

The data output register configuration is broken down into three

different functions: new data ready bit (ND), alarm indicator

(EA), and data bits (D0 to D13). The ND bit is used to determine

if a particular register has been updated since the last read

command. A Logic Level 1 for ND indicates that unread data is

available. When a register is read, this bit is set to a 0 logic level.

The alarm indicator provides users with a simple method for

passively monitoring a variety of status/alarm conditions and can

be used to simplify system-level processing requirements.

The two acceleration output data registers are 14 bits in length

and are formatted as twos complement binary numbers. The

rest of the data output registers are 12 bits in length, leaving D12

and D13 as “don’t care” bits. The output format for each of these

registers, along with their addresses, can be found in Table 7.

Each output data register has two different addresses. The first

address is for the upper byte, which contains the most

significant bits (D8 to D13), ND, and EA data. The second

address is for the lower byte, which contains the eight least

significant bits (D0 to D7). Reading either of these addresses

results in all 16 bits being clocked out on the DOUT line as

defined in Table 6 during the next SPI cycle.

ADDRESS

IDLE

NEXT COMMAND

BASED ON PREVIOUS COMMAND

16-BIT DATA WORD

SCLK

DIN

DOUT

READ BIT = 0

ZERO

Figure 34. Register Read Command Sequence

Table 6. Register Read Command Bit Map

DIN

W/R1

DOUT

D13

D12

D11

D10

Upper Byte

Lower Byte

1 The W/R bit is always 0 for read commands.

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